diff options
author | Andreas Gampe <agampe@google.com> | 2015-04-09 15:30:51 -0700 |
---|---|---|
committer | Andreas Gampe <agampe@google.com> | 2015-04-09 15:30:51 -0700 |
commit | 8f486f3d3f0215a468323f68d1ae30bc283e9bf6 (patch) | |
tree | 0f5ea7b11910fc1f7ecd315e31e67f0f31359fde | |
parent | 1751f38a8fca421b0d527dbaea3559b940451218 (diff) | |
download | art-8f486f3d3f0215a468323f68d1ae30bc283e9bf6.zip art-8f486f3d3f0215a468323f68d1ae30bc283e9bf6.tar.gz art-8f486f3d3f0215a468323f68d1ae30bc283e9bf6.tar.bz2 |
ART: Fix indent in Mips backend
Change-Id: Ib8bc6f6bf36079e0b6e4b65ceab8af7dedc60efc
-rw-r--r-- | compiler/dex/quick/mips/call_mips.cc | 112 | ||||
-rw-r--r-- | compiler/dex/quick/mips/int_mips.cc | 44 |
2 files changed, 78 insertions, 78 deletions
diff --git a/compiler/dex/quick/mips/call_mips.cc b/compiler/dex/quick/mips/call_mips.cc index 7d4f20e..05570e4 100644 --- a/compiler/dex/quick/mips/call_mips.cc +++ b/compiler/dex/quick/mips/call_mips.cc @@ -403,73 +403,73 @@ static int NextSDCallInsn(CompilationUnit* cu, CallInfo* info ATTRIBUTE_UNUSED, Mir2Lir* cg = static_cast<Mir2Lir*>(cu->cg.get()); if (direct_code != 0 && direct_method != 0) { switch (state) { - case 0: // Get the current Method* [sets kArg0] - if (direct_code != static_cast<uintptr_t>(-1)) { - if (cu->target64) { - cg->LoadConstantWide(cg->TargetPtrReg(kInvokeTgt), direct_code); + case 0: // Get the current Method* [sets kArg0] + if (direct_code != static_cast<uintptr_t>(-1)) { + if (cu->target64) { + cg->LoadConstantWide(cg->TargetPtrReg(kInvokeTgt), direct_code); + } else { + cg->LoadConstant(cg->TargetPtrReg(kInvokeTgt), direct_code); + } } else { - cg->LoadConstant(cg->TargetPtrReg(kInvokeTgt), direct_code); + cg->LoadCodeAddress(target_method, type, kInvokeTgt); } - } else { - cg->LoadCodeAddress(target_method, type, kInvokeTgt); - } - if (direct_method != static_cast<uintptr_t>(-1)) { - if (cu->target64) { - cg->LoadConstantWide(cg->TargetReg(kArg0, kRef), direct_method); + if (direct_method != static_cast<uintptr_t>(-1)) { + if (cu->target64) { + cg->LoadConstantWide(cg->TargetReg(kArg0, kRef), direct_method); + } else { + cg->LoadConstant(cg->TargetReg(kArg0, kRef), direct_method); + } } else { - cg->LoadConstant(cg->TargetReg(kArg0, kRef), direct_method); + cg->LoadMethodAddress(target_method, type, kArg0); } - } else { - cg->LoadMethodAddress(target_method, type, kArg0); - } - break; - default: - return -1; + break; + default: + return -1; } } else { RegStorage arg0_ref = cg->TargetReg(kArg0, kRef); switch (state) { - case 0: // Get the current Method* [sets kArg0] - // TUNING: we can save a reg copy if Method* has been promoted. - cg->LoadCurrMethodDirect(arg0_ref); - break; - case 1: // Get method->dex_cache_resolved_methods_ - cg->LoadRefDisp(arg0_ref, - mirror::ArtMethod::DexCacheResolvedMethodsOffset().Int32Value(), - arg0_ref, - kNotVolatile); - // Set up direct code if known. - if (direct_code != 0) { - if (direct_code != static_cast<uintptr_t>(-1)) { - if (cu->target64) { - cg->LoadConstantWide(cg->TargetPtrReg(kInvokeTgt), direct_code); + case 0: // Get the current Method* [sets kArg0] + // TUNING: we can save a reg copy if Method* has been promoted. + cg->LoadCurrMethodDirect(arg0_ref); + break; + case 1: // Get method->dex_cache_resolved_methods_ + cg->LoadRefDisp(arg0_ref, + mirror::ArtMethod::DexCacheResolvedMethodsOffset().Int32Value(), + arg0_ref, + kNotVolatile); + // Set up direct code if known. + if (direct_code != 0) { + if (direct_code != static_cast<uintptr_t>(-1)) { + if (cu->target64) { + cg->LoadConstantWide(cg->TargetPtrReg(kInvokeTgt), direct_code); + } else { + cg->LoadConstant(cg->TargetPtrReg(kInvokeTgt), direct_code); + } } else { - cg->LoadConstant(cg->TargetPtrReg(kInvokeTgt), direct_code); + CHECK_LT(target_method.dex_method_index, target_method.dex_file->NumMethodIds()); + cg->LoadCodeAddress(target_method, type, kInvokeTgt); } - } else { - CHECK_LT(target_method.dex_method_index, target_method.dex_file->NumMethodIds()); - cg->LoadCodeAddress(target_method, type, kInvokeTgt); } - } - break; - case 2: // Grab target method* - CHECK_EQ(cu->dex_file, target_method.dex_file); - cg->LoadRefDisp(arg0_ref, - mirror::ObjectArray<mirror::Object>:: - OffsetOfElement(target_method.dex_method_index).Int32Value(), - arg0_ref, - kNotVolatile); - break; - case 3: // Grab the code from the method* - if (direct_code == 0) { - int32_t offset = mirror::ArtMethod::EntryPointFromQuickCompiledCodeOffset( - InstructionSetPointerSize(cu->instruction_set)).Int32Value(); - // Get the compiled code address [use *alt_from or kArg0, set kInvokeTgt] - cg->LoadWordDisp(arg0_ref, offset, cg->TargetPtrReg(kInvokeTgt)); - } - break; - default: - return -1; + break; + case 2: // Grab target method* + CHECK_EQ(cu->dex_file, target_method.dex_file); + cg->LoadRefDisp(arg0_ref, + mirror::ObjectArray<mirror::Object>:: + OffsetOfElement(target_method.dex_method_index).Int32Value(), + arg0_ref, + kNotVolatile); + break; + case 3: // Grab the code from the method* + if (direct_code == 0) { + int32_t offset = mirror::ArtMethod::EntryPointFromQuickCompiledCodeOffset( + InstructionSetPointerSize(cu->instruction_set)).Int32Value(); + // Get the compiled code address [use *alt_from or kArg0, set kInvokeTgt] + cg->LoadWordDisp(arg0_ref, offset, cg->TargetPtrReg(kInvokeTgt)); + } + break; + default: + return -1; } } return state + 1; diff --git a/compiler/dex/quick/mips/int_mips.cc b/compiler/dex/quick/mips/int_mips.cc index 290a7bd..1ca8bb6 100644 --- a/compiler/dex/quick/mips/int_mips.cc +++ b/compiler/dex/quick/mips/int_mips.cc @@ -237,12 +237,12 @@ void MipsMir2Lir::OpRegCopyWide(RegStorage r_dest, RegStorage r_src) { // note the operands are swapped for the mtc1 and mthc1 instr. // Here if dest is fp reg and src is core reg. if (fpuIs32Bit_) { - NewLIR2(kMipsMtc1, r_src.GetLowReg(), r_dest.GetLowReg()); - NewLIR2(kMipsMtc1, r_src.GetHighReg(), r_dest.GetHighReg()); + NewLIR2(kMipsMtc1, r_src.GetLowReg(), r_dest.GetLowReg()); + NewLIR2(kMipsMtc1, r_src.GetHighReg(), r_dest.GetHighReg()); } else { - r_dest = Fp64ToSolo32(r_dest); - NewLIR2(kMipsMtc1, r_src.GetLowReg(), r_dest.GetReg()); - NewLIR2(kMipsMthc1, r_src.GetHighReg(), r_dest.GetReg()); + r_dest = Fp64ToSolo32(r_dest); + NewLIR2(kMipsMtc1, r_src.GetLowReg(), r_dest.GetReg()); + NewLIR2(kMipsMthc1, r_src.GetHighReg(), r_dest.GetReg()); } } } else { @@ -311,10 +311,10 @@ RegLocation MipsMir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg1, int RegStorage t_reg = AllocTemp(); // lit is guarantee to be a 16-bit constant if (IsUint<16>(lit)) { - NewLIR3(kMipsOri, t_reg.GetReg(), rZERO, lit); + NewLIR3(kMipsOri, t_reg.GetReg(), rZERO, lit); } else { - // Addiu will sign extend the entire width (32 or 64) of the register. - NewLIR3(kMipsAddiu, t_reg.GetReg(), rZERO, lit); + // Addiu will sign extend the entire width (32 or 64) of the register. + NewLIR3(kMipsAddiu, t_reg.GetReg(), rZERO, lit); } RegLocation rl_result = GenDivRem(rl_dest, reg1, t_reg, is_div); FreeTemp(t_reg); @@ -821,20 +821,20 @@ void MipsMir2Lir::GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, } OpKind op = kOpBkpt; switch (opcode) { - case Instruction::SHL_LONG: - case Instruction::SHL_LONG_2ADDR: - op = kOpLsl; - break; - case Instruction::SHR_LONG: - case Instruction::SHR_LONG_2ADDR: - op = kOpAsr; - break; - case Instruction::USHR_LONG: - case Instruction::USHR_LONG_2ADDR: - op = kOpLsr; - break; - default: - LOG(FATAL) << "Unexpected case: " << opcode; + case Instruction::SHL_LONG: + case Instruction::SHL_LONG_2ADDR: + op = kOpLsl; + break; + case Instruction::SHR_LONG: + case Instruction::SHR_LONG_2ADDR: + op = kOpAsr; + break; + case Instruction::USHR_LONG: + case Instruction::USHR_LONG_2ADDR: + op = kOpLsr; + break; + default: + LOG(FATAL) << "Unexpected case: " << opcode; } rl_shift = LoadValue(rl_shift, kCoreReg); rl_src1 = LoadValueWide(rl_src1, kCoreReg); |