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authorRazvan A Lupusoru <razvan.a.lupusoru@intel.com>2014-02-25 17:41:08 -0800
committerIan Rogers <irogers@google.com>2014-03-26 16:20:09 -0700
commit99ad7230ccaace93bf323dea9790f35fe991a4a2 (patch)
tree095705c674703953bf4c50f6a30a105420b770b5 /compiler/dex/compiler_enums.h
parenta9e3d2ccfdbf7f4c7b1508bcb2b774037399b1d4 (diff)
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Relaxed memory barriers for x86
X86 provides stronger memory guarantees and thus the memory barriers can be optimized. This patch ensures that all memory barriers for x86 are treated as scheduling barriers. And in cases where a barrier is needed (StoreLoad case), an mfence is used. Change-Id: I13d02bf3f152083ba9f358052aedb583b0d48640 Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
Diffstat (limited to 'compiler/dex/compiler_enums.h')
-rw-r--r--compiler/dex/compiler_enums.h12
1 files changed, 11 insertions, 1 deletions
diff --git a/compiler/dex/compiler_enums.h b/compiler/dex/compiler_enums.h
index 718468f..eb4a336 100644
--- a/compiler/dex/compiler_enums.h
+++ b/compiler/dex/compiler_enums.h
@@ -339,7 +339,16 @@ enum DividePattern {
std::ostream& operator<<(std::ostream& os, const DividePattern& pattern);
-// Memory barrier types (see "The JSR-133 Cookbook for Compiler Writers").
+/**
+ * @brief Memory barrier types (see "The JSR-133 Cookbook for Compiler Writers").
+ * @details Without context sensitive analysis, the most conservative set of barriers
+ * must be issued to ensure the Java Memory Model. Thus the recipe is as follows:
+ * -# Use StoreStore barrier before volatile store.
+ * -# Use StoreLoad barrier after volatile store.
+ * -# Use LoadLoad and LoadStore barrier after each volatile load.
+ * -# Use StoreStore barrier after all stores but before return from any constructor whose
+ * class has final fields.
+ */
enum MemBarrierKind {
kLoadStore,
kLoadLoad,
@@ -364,6 +373,7 @@ enum OpFeatureFlags {
kPCRelFixup, // x86 FIXME: add NEEDS_FIXUP to instruction attributes.
kRegDef0,
kRegDef1,
+ kRegDef2,
kRegDefA,
kRegDefD,
kRegDefFPCSList0,