diff options
author | Serban Constantinescu <serban.constantinescu@arm.com> | 2014-07-15 17:44:21 +0100 |
---|---|---|
committer | Serban Constantinescu <serban.constantinescu@arm.com> | 2014-07-28 19:17:30 +0100 |
commit | 63999683329612292d534e6be09dbde9480f1250 (patch) | |
tree | 4412a387d3fc4313f98138764ce9197f58f9825c /compiler/dex/quick/arm64/utility_arm64.cc | |
parent | 3f49507c333b7c8d36620870522a7a1055987ef8 (diff) | |
download | art-63999683329612292d534e6be09dbde9480f1250.zip art-63999683329612292d534e6be09dbde9480f1250.tar.gz art-63999683329612292d534e6be09dbde9480f1250.tar.bz2 |
Revert "Revert "Enable Load Store Elimination for ARM and ARM64""
This patch refactors the implementation of the LoadStoreElimination
optimisation pass. Please note that this pass was disabled and not
functional for any of the backends.
The current implementation tracks aliases and handles DalvikRegs as well
as Heap memory regions. It has been tested and it is known to optimise
out the following:
* Load - Load
* Store - Load
* Store - Store
* Load Literals
Change-Id: I3aadb12a787164146a95bc314e85fa73ad91e12b
Diffstat (limited to 'compiler/dex/quick/arm64/utility_arm64.cc')
-rw-r--r-- | compiler/dex/quick/arm64/utility_arm64.cc | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/compiler/dex/quick/arm64/utility_arm64.cc b/compiler/dex/quick/arm64/utility_arm64.cc index f6c140f..221dbfa 100644 --- a/compiler/dex/quick/arm64/utility_arm64.cc +++ b/compiler/dex/quick/arm64/utility_arm64.cc @@ -87,6 +87,26 @@ static int32_t EncodeImmDouble(uint64_t bits) { return (bit7 | bit6 | bit5_to_0); } +size_t Arm64Mir2Lir::GetLoadStoreSize(LIR* lir) { + bool opcode_is_wide = IS_WIDE(lir->opcode); + ArmOpcode opcode = UNWIDE(lir->opcode); + DCHECK(!IsPseudoLirOp(opcode)); + const ArmEncodingMap *encoder = &EncodingMap[opcode]; + uint32_t bits = opcode_is_wide ? encoder->xskeleton : encoder->wskeleton; + return (bits >> 30); +} + +size_t Arm64Mir2Lir::GetInstructionOffset(LIR* lir) { + size_t offset = lir->operands[2]; + uint64_t check_flags = GetTargetInstFlags(lir->opcode); + DCHECK((check_flags & IS_LOAD) || (check_flags & IS_STORE)); + if (check_flags & SCALED_OFFSET_X0) { + DCHECK(check_flags & IS_TERTIARY_OP); + offset = offset * (1 << GetLoadStoreSize(lir)); + } + return offset; +} + LIR* Arm64Mir2Lir::LoadFPConstantValue(RegStorage r_dest, int32_t value) { DCHECK(r_dest.IsSingle()); if (value == 0) { |