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author | nikolay serdjuk <nikolay.y.serdjuk@intel.com> | 2014-06-10 17:07:10 +0700 |
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committer | Andreas Gampe <agampe@google.com> | 2014-07-03 18:30:07 -0700 |
commit | c5e4ce116e4d44bfdf162f0c949e77772d7e0654 (patch) | |
tree | 00ecfcb695dc3f77c6802314d42700af286dc1c2 /compiler/dex/quick/x86/utility_x86.cc | |
parent | 03cbed6dfbd2750a243363ee4033c425d58cac6e (diff) | |
download | art-c5e4ce116e4d44bfdf162f0c949e77772d7e0654.zip art-c5e4ce116e4d44bfdf162f0c949e77772d7e0654.tar.gz art-c5e4ce116e4d44bfdf162f0c949e77772d7e0654.tar.bz2 |
x86_64: Fix intrinsics
The following intrinsics have been ported:
- Abs(double/long/int/float)
- String.indexOf/charAt/compareTo/is_empty/length
- Float.floatToRawIntBits, Float.intBitsToFloat
- Double.doubleToRawLongBits, Double.longBitsToDouble
- Thread.currentThread
- Unsafe.getInt/Long/Object, Unsafe.putInt/Long/Object
- Math.sqrt, Math.max, Math.min
- Long.reverseBytes
Math.min and max for longs have been implemented for x86_64.
Commented out until good tests available:
- Memory.peekShort/Int/Long, Memory.pokeShort/Int/Long
Turned off on x86-64 as reported having problems
- Cas
Change-Id: I934bc9c90fdf953be0d3836a17b6ee4e7c98f244
Diffstat (limited to 'compiler/dex/quick/x86/utility_x86.cc')
-rw-r--r-- | compiler/dex/quick/x86/utility_x86.cc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/compiler/dex/quick/x86/utility_x86.cc b/compiler/dex/quick/x86/utility_x86.cc index 4770ade..657160f 100644 --- a/compiler/dex/quick/x86/utility_x86.cc +++ b/compiler/dex/quick/x86/utility_x86.cc @@ -122,7 +122,7 @@ LIR* X86Mir2Lir::OpReg(OpKind op, RegStorage r_dest_src) { switch (op) { case kOpNeg: opcode = r_dest_src.Is64Bit() ? kX86Neg64R : kX86Neg32R; break; case kOpNot: opcode = r_dest_src.Is64Bit() ? kX86Not64R : kX86Not32R; break; - case kOpRev: opcode = kX86Bswap32R; break; + case kOpRev: opcode = r_dest_src.Is64Bit() ? kX86Bswap64R : kX86Bswap32R; break; case kOpBlx: opcode = kX86CallR; break; default: LOG(FATAL) << "Bad case in OpReg " << op; @@ -356,7 +356,9 @@ LIR* X86Mir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, Mo LIR* X86Mir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) { // The only conditional reg to reg operation supported is Cmov DCHECK_EQ(op, kOpCmov); - return NewLIR3(kX86Cmov32RRC, r_dest.GetReg(), r_src.GetReg(), X86ConditionEncoding(cc)); + DCHECK_EQ(r_dest.Is64Bit(), r_src.Is64Bit()); + return NewLIR3(r_dest.Is64Bit() ? kX86Cmov64RRC : kX86Cmov32RRC, r_dest.GetReg(), + r_src.GetReg(), X86ConditionEncoding(cc)); } LIR* X86Mir2Lir::OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset) { |