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authorAndreas Gampe <agampe@google.com>2015-04-09 22:09:29 +0000
committerGerrit Code Review <noreply-gerritcodereview@google.com>2015-04-09 22:09:29 +0000
commit1751f38a8fca421b0d527dbaea3559b940451218 (patch)
tree360ba19654ecd5158925dfe5f54328b82eb47891 /compiler/dex/quick
parent66bae2f3039061775c9d39bae95287078423cf20 (diff)
parent7fa6e279dfda5b2f21e4c234f562a49a5fe5d218 (diff)
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Merge "Fix GenDivRemLit() for Mips."
Diffstat (limited to 'compiler/dex/quick')
-rw-r--r--compiler/dex/quick/mips/int_mips.cc8
1 files changed, 7 insertions, 1 deletions
diff --git a/compiler/dex/quick/mips/int_mips.cc b/compiler/dex/quick/mips/int_mips.cc
index 626b36e..290a7bd 100644
--- a/compiler/dex/quick/mips/int_mips.cc
+++ b/compiler/dex/quick/mips/int_mips.cc
@@ -309,7 +309,13 @@ RegLocation MipsMir2Lir::GenDivRem(RegLocation rl_dest, RegStorage reg1, RegStor
RegLocation MipsMir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg1, int lit, bool is_div) {
RegStorage t_reg = AllocTemp();
- NewLIR3(kMipsAddiu, t_reg.GetReg(), rZERO, lit);
+ // lit is guarantee to be a 16-bit constant
+ if (IsUint<16>(lit)) {
+ NewLIR3(kMipsOri, t_reg.GetReg(), rZERO, lit);
+ } else {
+ // Addiu will sign extend the entire width (32 or 64) of the register.
+ NewLIR3(kMipsAddiu, t_reg.GetReg(), rZERO, lit);
+ }
RegLocation rl_result = GenDivRem(rl_dest, reg1, t_reg, is_div);
FreeTemp(t_reg);
return rl_result;