Fix cpplint whitespace/indent issues

Change-Id: I7c1647f0c39e1e065ca5820f9b79998691ba40b1

9 files changed, 249 insertions, 249 deletions

diff --git a/compiler/dex/mir_graph.h b/compiler/dex/mir_graph.h
index f6011e0..9c63d9c 100644
--- a/compiler/dex/mir_graph.h
+++ b/compiler/dex/mir_graph.h
@@ -542,120 +542,120 @@ class MIRGraph {
    * IsDebugBuild sanity check: keep track of the Dex PCs for catch entries so that later on
    * we can verify that all catch entries have native PC entries.
    */
-   std::set<uint32_t> catches_;
+  std::set<uint32_t> catches_;
 
-   // TODO: make these private.
-   RegLocation* reg_location_;                         // Map SSA names to location.
-   GrowableArray<CompilerTemp*> compiler_temps_;
-   SafeMap<unsigned int, unsigned int> block_id_map_;  // Block collapse lookup cache.
+  // TODO: make these private.
+  RegLocation* reg_location_;                         // Map SSA names to location.
+  GrowableArray<CompilerTemp*> compiler_temps_;
+  SafeMap<unsigned int, unsigned int> block_id_map_;  // Block collapse lookup cache.
 
-   static const int oat_data_flow_attributes_[kMirOpLast];
-   static const char* extended_mir_op_names_[kMirOpLast - kMirOpFirst];
+  static const int oat_data_flow_attributes_[kMirOpLast];
+  static const char* extended_mir_op_names_[kMirOpLast - kMirOpFirst];
 
  private:
-   int FindCommonParent(int block1, int block2);
-   void ComputeSuccLineIn(ArenaBitVector* dest, const ArenaBitVector* src1,
-                          const ArenaBitVector* src2);
-   void HandleLiveInUse(ArenaBitVector* use_v, ArenaBitVector* def_v,
-                        ArenaBitVector* live_in_v, int dalvik_reg_id);
-   void HandleDef(ArenaBitVector* def_v, int dalvik_reg_id);
-   void CompilerInitializeSSAConversion();
-   bool DoSSAConversion(BasicBlock* bb);
-   bool InvokeUsesMethodStar(MIR* mir);
-   int ParseInsn(const uint16_t* code_ptr, DecodedInstruction* decoded_instruction);
-   bool ContentIsInsn(const uint16_t* code_ptr);
-   BasicBlock* SplitBlock(unsigned int code_offset, BasicBlock* orig_block,
-                          BasicBlock** immed_pred_block_p);
-   BasicBlock* FindBlock(unsigned int code_offset, bool split, bool create,
+  int FindCommonParent(int block1, int block2);
+  void ComputeSuccLineIn(ArenaBitVector* dest, const ArenaBitVector* src1,
+                         const ArenaBitVector* src2);
+  void HandleLiveInUse(ArenaBitVector* use_v, ArenaBitVector* def_v,
+                       ArenaBitVector* live_in_v, int dalvik_reg_id);
+  void HandleDef(ArenaBitVector* def_v, int dalvik_reg_id);
+  void CompilerInitializeSSAConversion();
+  bool DoSSAConversion(BasicBlock* bb);
+  bool InvokeUsesMethodStar(MIR* mir);
+  int ParseInsn(const uint16_t* code_ptr, DecodedInstruction* decoded_instruction);
+  bool ContentIsInsn(const uint16_t* code_ptr);
+  BasicBlock* SplitBlock(unsigned int code_offset, BasicBlock* orig_block,
                          BasicBlock** immed_pred_block_p);
-   void ProcessTryCatchBlocks();
-   BasicBlock* ProcessCanBranch(BasicBlock* cur_block, MIR* insn, int cur_offset, int width,
-                                int flags, const uint16_t* code_ptr, const uint16_t* code_end);
-   void ProcessCanSwitch(BasicBlock* cur_block, MIR* insn, int cur_offset, int width, int flags);
-   BasicBlock* ProcessCanThrow(BasicBlock* cur_block, MIR* insn, int cur_offset, int width,
-                               int flags, ArenaBitVector* try_block_addr, const uint16_t* code_ptr,
-                               const uint16_t* code_end);
-   int AddNewSReg(int v_reg);
-   void HandleSSAUse(int* uses, int dalvik_reg, int reg_index);
-   void HandleSSADef(int* defs, int dalvik_reg, int reg_index);
-   void DataFlowSSAFormat35C(MIR* mir);
-   void DataFlowSSAFormat3RC(MIR* mir);
-   bool FindLocalLiveIn(BasicBlock* bb);
-   void ClearAllVisitedFlags();
-   bool CountUses(struct BasicBlock* bb);
-   bool InferTypeAndSize(BasicBlock* bb);
-   bool VerifyPredInfo(BasicBlock* bb);
-   BasicBlock* NeedsVisit(BasicBlock* bb);
-   BasicBlock* NextUnvisitedSuccessor(BasicBlock* bb);
-   void MarkPreOrder(BasicBlock* bb);
-   void RecordDFSOrders(BasicBlock* bb);
-   void ComputeDFSOrders();
-   void ComputeDefBlockMatrix();
-   void ComputeDomPostOrderTraversal(BasicBlock* bb);
-   void ComputeDominators();
-   void InsertPhiNodes();
-   void DoDFSPreOrderSSARename(BasicBlock* block);
-   void SetConstant(int32_t ssa_reg, int value);
-   void SetConstantWide(int ssa_reg, int64_t value);
-   int GetSSAUseCount(int s_reg);
-   bool BasicBlockOpt(BasicBlock* bb);
-   bool EliminateNullChecks(BasicBlock* bb);
-   void NullCheckEliminationInit(BasicBlock* bb);
-   bool BuildExtendedBBList(struct BasicBlock* bb);
-   bool FillDefBlockMatrix(BasicBlock* bb);
-   void InitializeDominationInfo(BasicBlock* bb);
-   bool ComputeblockIDom(BasicBlock* bb);
-   bool ComputeBlockDominators(BasicBlock* bb);
-   bool SetDominators(BasicBlock* bb);
-   bool ComputeBlockLiveIns(BasicBlock* bb);
-   bool InsertPhiNodeOperands(BasicBlock* bb);
-   bool ComputeDominanceFrontier(BasicBlock* bb);
-   void DoConstantPropogation(BasicBlock* bb);
-   void CountChecks(BasicBlock* bb);
-   bool CombineBlocks(BasicBlock* bb);
-
-   CompilationUnit* const cu_;
-   GrowableArray<int>* ssa_base_vregs_;
-   GrowableArray<int>* ssa_subscripts_;
-   // Map original Dalvik virtual reg i to the current SSA name.
-   int* vreg_to_ssa_map_;            // length == method->registers_size
-   int* ssa_last_defs_;              // length == method->registers_size
-   ArenaBitVector* is_constant_v_;   // length == num_ssa_reg
-   int* constant_values_;            // length == num_ssa_reg
-   // Use counts of ssa names.
-   GrowableArray<uint32_t> use_counts_;      // Weighted by nesting depth
-   GrowableArray<uint32_t> raw_use_counts_;  // Not weighted
-   unsigned int num_reachable_blocks_;
-   GrowableArray<int>* dfs_order_;
-   GrowableArray<int>* dfs_post_order_;
-   GrowableArray<int>* dom_post_order_traversal_;
-   int* i_dom_list_;
-   ArenaBitVector** def_block_matrix_;    // num_dalvik_register x num_blocks.
-   ArenaBitVector* temp_block_v_;
-   ArenaBitVector* temp_dalvik_register_v_;
-   ArenaBitVector* temp_ssa_register_v_;  // num_ssa_regs.
-   static const int kInvalidEntry = -1;
-   GrowableArray<BasicBlock*> block_list_;
-   ArenaBitVector* try_block_addr_;
-   BasicBlock* entry_block_;
-   BasicBlock* exit_block_;
-   BasicBlock* cur_block_;
-   int num_blocks_;
-   const DexFile::CodeItem* current_code_item_;
-   SafeMap<unsigned int, BasicBlock*> block_map_; // FindBlock lookup cache.
-   std::vector<DexCompilationUnit*> m_units_;     // List of methods included in this graph
-   typedef std::pair<int, int> MIRLocation;       // Insert point, (m_unit_ index, offset)
-   std::vector<MIRLocation> method_stack_;        // Include stack
-   int current_method_;
-   int current_offset_;
-   int def_count_;                                // Used to estimate size of ssa name storage.
-   int* opcode_count_;                            // Dex opcode coverage stats.
-   int num_ssa_regs_;                             // Number of names following SSA transformation.
-   std::vector<BasicBlock*> extended_basic_blocks_; // Heads of block "traces".
-   int method_sreg_;
-   unsigned int attributes_;
-   Checkstats* checkstats_;
-   ArenaAllocator* arena_;
+  BasicBlock* FindBlock(unsigned int code_offset, bool split, bool create,
+                        BasicBlock** immed_pred_block_p);
+  void ProcessTryCatchBlocks();
+  BasicBlock* ProcessCanBranch(BasicBlock* cur_block, MIR* insn, int cur_offset, int width,
+                               int flags, const uint16_t* code_ptr, const uint16_t* code_end);
+  void ProcessCanSwitch(BasicBlock* cur_block, MIR* insn, int cur_offset, int width, int flags);
+  BasicBlock* ProcessCanThrow(BasicBlock* cur_block, MIR* insn, int cur_offset, int width,
+                              int flags, ArenaBitVector* try_block_addr, const uint16_t* code_ptr,
+                              const uint16_t* code_end);
+  int AddNewSReg(int v_reg);
+  void HandleSSAUse(int* uses, int dalvik_reg, int reg_index);
+  void HandleSSADef(int* defs, int dalvik_reg, int reg_index);
+  void DataFlowSSAFormat35C(MIR* mir);
+  void DataFlowSSAFormat3RC(MIR* mir);
+  bool FindLocalLiveIn(BasicBlock* bb);
+  void ClearAllVisitedFlags();
+  bool CountUses(struct BasicBlock* bb);
+  bool InferTypeAndSize(BasicBlock* bb);
+  bool VerifyPredInfo(BasicBlock* bb);
+  BasicBlock* NeedsVisit(BasicBlock* bb);
+  BasicBlock* NextUnvisitedSuccessor(BasicBlock* bb);
+  void MarkPreOrder(BasicBlock* bb);
+  void RecordDFSOrders(BasicBlock* bb);
+  void ComputeDFSOrders();
+  void ComputeDefBlockMatrix();
+  void ComputeDomPostOrderTraversal(BasicBlock* bb);
+  void ComputeDominators();
+  void InsertPhiNodes();
+  void DoDFSPreOrderSSARename(BasicBlock* block);
+  void SetConstant(int32_t ssa_reg, int value);
+  void SetConstantWide(int ssa_reg, int64_t value);
+  int GetSSAUseCount(int s_reg);
+  bool BasicBlockOpt(BasicBlock* bb);
+  bool EliminateNullChecks(BasicBlock* bb);
+  void NullCheckEliminationInit(BasicBlock* bb);
+  bool BuildExtendedBBList(struct BasicBlock* bb);
+  bool FillDefBlockMatrix(BasicBlock* bb);
+  void InitializeDominationInfo(BasicBlock* bb);
+  bool ComputeblockIDom(BasicBlock* bb);
+  bool ComputeBlockDominators(BasicBlock* bb);
+  bool SetDominators(BasicBlock* bb);
+  bool ComputeBlockLiveIns(BasicBlock* bb);
+  bool InsertPhiNodeOperands(BasicBlock* bb);
+  bool ComputeDominanceFrontier(BasicBlock* bb);
+  void DoConstantPropogation(BasicBlock* bb);
+  void CountChecks(BasicBlock* bb);
+  bool CombineBlocks(BasicBlock* bb);
+
+  CompilationUnit* const cu_;
+  GrowableArray<int>* ssa_base_vregs_;
+  GrowableArray<int>* ssa_subscripts_;
+  // Map original Dalvik virtual reg i to the current SSA name.
+  int* vreg_to_ssa_map_;            // length == method->registers_size
+  int* ssa_last_defs_;              // length == method->registers_size
+  ArenaBitVector* is_constant_v_;   // length == num_ssa_reg
+  int* constant_values_;            // length == num_ssa_reg
+  // Use counts of ssa names.
+  GrowableArray<uint32_t> use_counts_;      // Weighted by nesting depth
+  GrowableArray<uint32_t> raw_use_counts_;  // Not weighted
+  unsigned int num_reachable_blocks_;
+  GrowableArray<int>* dfs_order_;
+  GrowableArray<int>* dfs_post_order_;
+  GrowableArray<int>* dom_post_order_traversal_;
+  int* i_dom_list_;
+  ArenaBitVector** def_block_matrix_;    // num_dalvik_register x num_blocks.
+  ArenaBitVector* temp_block_v_;
+  ArenaBitVector* temp_dalvik_register_v_;
+  ArenaBitVector* temp_ssa_register_v_;  // num_ssa_regs.
+  static const int kInvalidEntry = -1;
+  GrowableArray<BasicBlock*> block_list_;
+  ArenaBitVector* try_block_addr_;
+  BasicBlock* entry_block_;
+  BasicBlock* exit_block_;
+  BasicBlock* cur_block_;
+  int num_blocks_;
+  const DexFile::CodeItem* current_code_item_;
+  SafeMap<unsigned int, BasicBlock*> block_map_; // FindBlock lookup cache.
+  std::vector<DexCompilationUnit*> m_units_;     // List of methods included in this graph
+  typedef std::pair<int, int> MIRLocation;       // Insert point, (m_unit_ index, offset)
+  std::vector<MIRLocation> method_stack_;        // Include stack
+  int current_method_;
+  int current_offset_;
+  int def_count_;                                // Used to estimate size of ssa name storage.
+  int* opcode_count_;                            // Dex opcode coverage stats.
+  int num_ssa_regs_;                             // Number of names following SSA transformation.
+  std::vector<BasicBlock*> extended_basic_blocks_; // Heads of block "traces".
+  int method_sreg_;
+  unsigned int attributes_;
+  Checkstats* checkstats_;
+  ArenaAllocator* arena_;
 };
 
 }  // namespace art
diff --git a/compiler/dex/mir_optimization.cc b/compiler/dex/mir_optimization.cc
index f83bbb2..22c738a 100644
--- a/compiler/dex/mir_optimization.cc
+++ b/compiler/dex/mir_optimization.cc
@@ -183,15 +183,15 @@ static SelectInstructionKind SelectKind(MIR* mir) {
     case Instruction::MOVE_FROM16:
     case Instruction::MOVE_OBJECT_FROM16:
       return kSelectMove;
-   case Instruction::CONST:
-   case Instruction::CONST_4:
-   case Instruction::CONST_16:
+    case Instruction::CONST:
+    case Instruction::CONST_4:
+    case Instruction::CONST_16:
       return kSelectConst;
-   case Instruction::GOTO:
-   case Instruction::GOTO_16:
-   case Instruction::GOTO_32:
+    case Instruction::GOTO:
+    case Instruction::GOTO_16:
+    case Instruction::GOTO_32:
       return kSelectGoto;
-   default:;
+    default:;
   }
   return kSelectNone;
 }
diff --git a/compiler/dex/portable/mir_to_gbc.cc b/compiler/dex/portable/mir_to_gbc.cc
index ad7a6a8..6fc01bd 100644
--- a/compiler/dex/portable/mir_to_gbc.cc
+++ b/compiler/dex/portable/mir_to_gbc.cc
@@ -1179,11 +1179,11 @@ bool MirConverter::ConvertMIRNode(MIR* mir, BasicBlock* bb,
       ConvertNewInstance(vB, rl_dest);
       break;
 
-   case Instruction::MOVE_EXCEPTION:
+    case Instruction::MOVE_EXCEPTION:
       ConvertMoveException(rl_dest);
       break;
 
-   case Instruction::THROW:
+    case Instruction::THROW:
       ConvertThrow(rl_src[0]);
       /*
        * If this throw is standalone, terminate.
diff --git a/compiler/dex/quick/arm/call_arm.cc b/compiler/dex/quick/arm/call_arm.cc
index 0e81324..1416c61 100644
--- a/compiler/dex/quick/arm/call_arm.cc
+++ b/compiler/dex/quick/arm/call_arm.cc
@@ -217,63 +217,63 @@ MIR* ArmMir2Lir::SpecialIdentity(MIR* mir) {
  */
 void ArmMir2Lir::GenSpecialCase(BasicBlock* bb, MIR* mir,
                                 SpecialCaseHandler special_case) {
-   current_dalvik_offset_ = mir->offset;
-   MIR* next_mir = NULL;
-   switch (special_case) {
-     case kNullMethod:
-       DCHECK(mir->dalvikInsn.opcode == Instruction::RETURN_VOID);
-       next_mir = mir;
-       break;
-     case kConstFunction:
-       ArmMir2Lir::GenPrintLabel(mir);
-       LoadConstant(rARM_RET0, mir->dalvikInsn.vB);
-       next_mir = GetNextMir(&bb, mir);
-       break;
-     case kIGet:
-       next_mir = SpecialIGet(&bb, mir, kWord, false, false);
-       break;
-     case kIGetBoolean:
-     case kIGetByte:
-       next_mir = SpecialIGet(&bb, mir, kUnsignedByte, false, false);
-       break;
-     case kIGetObject:
-       next_mir = SpecialIGet(&bb, mir, kWord, false, true);
-       break;
-     case kIGetChar:
-       next_mir = SpecialIGet(&bb, mir, kUnsignedHalf, false, false);
-       break;
-     case kIGetShort:
-       next_mir = SpecialIGet(&bb, mir, kSignedHalf, false, false);
-       break;
-     case kIGetWide:
-       next_mir = SpecialIGet(&bb, mir, kLong, true, false);
-       break;
-     case kIPut:
-       next_mir = SpecialIPut(&bb, mir, kWord, false, false);
-       break;
-     case kIPutBoolean:
-     case kIPutByte:
-       next_mir = SpecialIPut(&bb, mir, kUnsignedByte, false, false);
-       break;
-     case kIPutObject:
-       next_mir = SpecialIPut(&bb, mir, kWord, false, true);
-       break;
-     case kIPutChar:
-       next_mir = SpecialIPut(&bb, mir, kUnsignedHalf, false, false);
-       break;
-     case kIPutShort:
-       next_mir = SpecialIPut(&bb, mir, kSignedHalf, false, false);
-       break;
-     case kIPutWide:
-       next_mir = SpecialIPut(&bb, mir, kLong, true, false);
-       break;
-     case kIdentity:
-       next_mir = SpecialIdentity(mir);
-       break;
-     default:
-       return;
-   }
-   if (next_mir != NULL) {
+  current_dalvik_offset_ = mir->offset;
+  MIR* next_mir = NULL;
+  switch (special_case) {
+    case kNullMethod:
+      DCHECK(mir->dalvikInsn.opcode == Instruction::RETURN_VOID);
+      next_mir = mir;
+      break;
+    case kConstFunction:
+      ArmMir2Lir::GenPrintLabel(mir);
+      LoadConstant(rARM_RET0, mir->dalvikInsn.vB);
+      next_mir = GetNextMir(&bb, mir);
+      break;
+    case kIGet:
+      next_mir = SpecialIGet(&bb, mir, kWord, false, false);
+      break;
+    case kIGetBoolean:
+    case kIGetByte:
+      next_mir = SpecialIGet(&bb, mir, kUnsignedByte, false, false);
+      break;
+    case kIGetObject:
+      next_mir = SpecialIGet(&bb, mir, kWord, false, true);
+      break;
+    case kIGetChar:
+      next_mir = SpecialIGet(&bb, mir, kUnsignedHalf, false, false);
+      break;
+    case kIGetShort:
+      next_mir = SpecialIGet(&bb, mir, kSignedHalf, false, false);
+      break;
+    case kIGetWide:
+      next_mir = SpecialIGet(&bb, mir, kLong, true, false);
+      break;
+    case kIPut:
+      next_mir = SpecialIPut(&bb, mir, kWord, false, false);
+      break;
+    case kIPutBoolean:
+    case kIPutByte:
+      next_mir = SpecialIPut(&bb, mir, kUnsignedByte, false, false);
+      break;
+    case kIPutObject:
+      next_mir = SpecialIPut(&bb, mir, kWord, false, true);
+      break;
+    case kIPutChar:
+      next_mir = SpecialIPut(&bb, mir, kUnsignedHalf, false, false);
+      break;
+    case kIPutShort:
+      next_mir = SpecialIPut(&bb, mir, kSignedHalf, false, false);
+      break;
+    case kIPutWide:
+      next_mir = SpecialIPut(&bb, mir, kLong, true, false);
+      break;
+    case kIdentity:
+      next_mir = SpecialIdentity(mir);
+      break;
+    default:
+      return;
+  }
+  if (next_mir != NULL) {
     current_dalvik_offset_ = next_mir->offset;
     if (special_case != kIdentity) {
       ArmMir2Lir::GenPrintLabel(next_mir);
diff --git a/compiler/dex/quick/arm/utility_arm.cc b/compiler/dex/quick/arm/utility_arm.cc
index f41f110..1ea0a64 100644
--- a/compiler/dex/quick/arm/utility_arm.cc
+++ b/compiler/dex/quick/arm/utility_arm.cc
@@ -118,32 +118,32 @@ static int LeadingZeros(uint32_t val) {
  * immediate.  If not, return -1.  If so, return i:imm3:a:bcdefgh form.
  */
 int ArmMir2Lir::ModifiedImmediate(uint32_t value) {
-   int z_leading;
-   int z_trailing;
-   uint32_t b0 = value & 0xff;
+  int z_leading;
+  int z_trailing;
+  uint32_t b0 = value & 0xff;
 
-   /* Note: case of value==0 must use 0:000:0:0000000 encoding */
-   if (value <= 0xFF)
-     return b0;  // 0:000:a:bcdefgh
-   if (value == ((b0 << 16) | b0))
-     return (0x1 << 8) | b0; /* 0:001:a:bcdefgh */
-   if (value == ((b0 << 24) | (b0 << 16) | (b0 << 8) | b0))
-     return (0x3 << 8) | b0; /* 0:011:a:bcdefgh */
-   b0 = (value >> 8) & 0xff;
-   if (value == ((b0 << 24) | (b0 << 8)))
-     return (0x2 << 8) | b0; /* 0:010:a:bcdefgh */
-   /* Can we do it with rotation? */
-   z_leading = LeadingZeros(value);
-   z_trailing = 32 - LeadingZeros(~value & (value - 1));
-   /* A run of eight or fewer active bits? */
-   if ((z_leading + z_trailing) < 24)
-     return -1;  /* No - bail */
-   /* left-justify the constant, discarding msb (known to be 1) */
-   value <<= z_leading + 1;
-   /* Create bcdefgh */
-   value >>= 25;
-   /* Put it all together */
-   return value | ((0x8 + z_leading) << 7); /* [01000..11111]:bcdefgh */
+  /* Note: case of value==0 must use 0:000:0:0000000 encoding */
+  if (value <= 0xFF)
+    return b0;  // 0:000:a:bcdefgh
+  if (value == ((b0 << 16) | b0))
+    return (0x1 << 8) | b0; /* 0:001:a:bcdefgh */
+  if (value == ((b0 << 24) | (b0 << 16) | (b0 << 8) | b0))
+    return (0x3 << 8) | b0; /* 0:011:a:bcdefgh */
+  b0 = (value >> 8) & 0xff;
+  if (value == ((b0 << 24) | (b0 << 8)))
+    return (0x2 << 8) | b0; /* 0:010:a:bcdefgh */
+  /* Can we do it with rotation? */
+  z_leading = LeadingZeros(value);
+  z_trailing = 32 - LeadingZeros(~value & (value - 1));
+  /* A run of eight or fewer active bits? */
+  if ((z_leading + z_trailing) < 24)
+    return -1;  /* No - bail */
+  /* left-justify the constant, discarding msb (known to be 1) */
+  value <<= z_leading + 1;
+  /* Create bcdefgh */
+  value >>= 25;
+  /* Put it all together */
+  return value | ((0x8 + z_leading) << 7); /* [01000..11111]:bcdefgh */
 }
 
 bool ArmMir2Lir::InexpensiveConstantInt(int32_t value) {
diff --git a/compiler/dex/quick/gen_common.cc b/compiler/dex/quick/gen_common.cc
index d1bfd2d..bc49b70 100644
--- a/compiler/dex/quick/gen_common.cc
+++ b/compiler/dex/quick/gen_common.cc
@@ -180,24 +180,24 @@ void Mir2Lir::GenIntToLong(RegLocation rl_dest, RegLocation rl_src) {
 
 void Mir2Lir::GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest,
                               RegLocation rl_src) {
-   rl_src = LoadValue(rl_src, kCoreReg);
-   RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
-   OpKind op = kOpInvalid;
-   switch (opcode) {
-     case Instruction::INT_TO_BYTE:
-       op = kOp2Byte;
+  rl_src = LoadValue(rl_src, kCoreReg);
+  RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
+  OpKind op = kOpInvalid;
+  switch (opcode) {
+    case Instruction::INT_TO_BYTE:
+      op = kOp2Byte;
+      break;
+    case Instruction::INT_TO_SHORT:
+       op = kOp2Short;
        break;
-     case Instruction::INT_TO_SHORT:
-        op = kOp2Short;
-        break;
-     case Instruction::INT_TO_CHAR:
-        op = kOp2Char;
-        break;
-     default:
-       LOG(ERROR) << "Bad int conversion type";
-   }
-   OpRegReg(op, rl_result.low_reg, rl_src.low_reg);
-   StoreValue(rl_dest, rl_result);
+    case Instruction::INT_TO_CHAR:
+       op = kOp2Char;
+       break;
+    default:
+      LOG(ERROR) << "Bad int conversion type";
+  }
+  OpRegReg(op, rl_result.low_reg, rl_src.low_reg);
+  StoreValue(rl_dest, rl_result);
 }
 
 /*
diff --git a/compiler/dex/quick/gen_invoke.cc b/compiler/dex/quick/gen_invoke.cc
index fd8f86b..8840526 100644
--- a/compiler/dex/quick/gen_invoke.cc
+++ b/compiler/dex/quick/gen_invoke.cc
@@ -877,7 +877,7 @@ bool Mir2Lir::GenInlinedCharAt(CallInfo* info) {
       OpRegReg(kOpCmp, rl_idx.low_reg, reg_max);
       FreeTemp(reg_max);
       OpCondBranch(kCondCs, launch_pad);
-   }
+    }
   } else {
     if (range_check) {
       reg_max = AllocTemp();
diff --git a/compiler/dex/quick/mir_to_lir.h b/compiler/dex/quick/mir_to_lir.h
index 0962167..4774456 100644
--- a/compiler/dex/quick/mir_to_lir.h
+++ b/compiler/dex/quick/mir_to_lir.h
@@ -208,14 +208,14 @@ class Mir2Lir : public Backend {
       LIR *def_end;               // Ending inst in last def sequence.
     };
 
-   struct RegisterPool {
-      int num_core_regs;
-      RegisterInfo *core_regs;
-      int next_core_reg;
-      int num_fp_regs;
-      RegisterInfo *FPRegs;
-      int next_fp_reg;
-    };
+    struct RegisterPool {
+       int num_core_regs;
+       RegisterInfo *core_regs;
+       int next_core_reg;
+       int num_fp_regs;
+       RegisterInfo *FPRegs;
+       int next_fp_reg;
+     };
 
     struct PromotionMap {
       RegLocationType core_location:3;
diff --git a/compiler/dex/quick/ralloc_util.cc b/compiler/dex/quick/ralloc_util.cc
index 67989a1..92bd94e 100644
--- a/compiler/dex/quick/ralloc_util.cc
+++ b/compiler/dex/quick/ralloc_util.cc
@@ -714,29 +714,29 @@ void Mir2Lir::CopyRegInfo(int new_reg, int old_reg) {
 }
 
 bool Mir2Lir::CheckCorePoolSanity() {
-   for (static int i = 0; i < reg_pool_->num_core_regs; i++) {
-     if (reg_pool_->core_regs[i].pair) {
-       static int my_reg = reg_pool_->core_regs[i].reg;
-       static int my_sreg = reg_pool_->core_regs[i].s_reg;
-       static int partner_reg = reg_pool_->core_regs[i].partner;
-       static RegisterInfo* partner = GetRegInfo(partner_reg);
-       DCHECK(partner != NULL);
-       DCHECK(partner->pair);
-       DCHECK_EQ(my_reg, partner->partner);
-       static int partner_sreg = partner->s_reg;
-       if (my_sreg == INVALID_SREG) {
-         DCHECK_EQ(partner_sreg, INVALID_SREG);
-       } else {
-         int diff = my_sreg - partner_sreg;
-         DCHECK((diff == -1) || (diff == 1));
-       }
-     }
-     if (!reg_pool_->core_regs[i].live) {
-       DCHECK(reg_pool_->core_regs[i].def_start == NULL);
-       DCHECK(reg_pool_->core_regs[i].def_end == NULL);
-     }
-   }
-   return true;
+  for (static int i = 0; i < reg_pool_->num_core_regs; i++) {
+    if (reg_pool_->core_regs[i].pair) {
+      static int my_reg = reg_pool_->core_regs[i].reg;
+      static int my_sreg = reg_pool_->core_regs[i].s_reg;
+      static int partner_reg = reg_pool_->core_regs[i].partner;
+      static RegisterInfo* partner = GetRegInfo(partner_reg);
+      DCHECK(partner != NULL);
+      DCHECK(partner->pair);
+      DCHECK_EQ(my_reg, partner->partner);
+      static int partner_sreg = partner->s_reg;
+      if (my_sreg == INVALID_SREG) {
+        DCHECK_EQ(partner_sreg, INVALID_SREG);
+      } else {
+        int diff = my_sreg - partner_sreg;
+        DCHECK((diff == -1) || (diff == 1));
+      }
+    }
+    if (!reg_pool_->core_regs[i].live) {
+      DCHECK(reg_pool_->core_regs[i].def_start == NULL);
+      DCHECK(reg_pool_->core_regs[i].def_end == NULL);
+    }
+  }
+  return true;
 }
 
 /*