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| author | Razvan A Lupusoru <razvan.a.lupusoru@intel.com> | 2014-09-23 14:54:32 -0700 |
|---|---|---|
| committer | Razvan A Lupusoru <razvan.a.lupusoru@intel.com> | 2014-09-29 09:44:50 -0700 |
| commit | ae9f3e6ef9f97f47416f829448e5281e9a57d8b8 (patch) | |
| tree | 75ca2f18379d514d15593e41c499f50a30d83130 /compiler/dex | |
| parent | c70535b4f9f1ff3e3da451734bb7d9601012ccc1 (diff) | |
| download | art-ae9f3e6ef9f97f47416f829448e5281e9a57d8b8.zip art-ae9f3e6ef9f97f47416f829448e5281e9a57d8b8.tar.gz art-ae9f3e6ef9f97f47416f829448e5281e9a57d8b8.tar.bz2 | |
ART: Fix movnti assembler
Movnti was receiving rex prefix before its opcode. Additionally,
the 64-bit version was missing the rex.w prefix.
Change-Id: Ie5c3bbe109765a0b990cafeeea1ee30329daabd0
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
Diffstat (limited to 'compiler/dex')
| -rw-r--r-- | compiler/dex/quick/x86/assemble_x86.cc | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/compiler/dex/quick/x86/assemble_x86.cc b/compiler/dex/quick/x86/assemble_x86.cc index a9a0252..ab1608b 100644 --- a/compiler/dex/quick/x86/assemble_x86.cc +++ b/compiler/dex/quick/x86/assemble_x86.cc @@ -189,8 +189,8 @@ ENCODING_MAP(Cmp, IS_LOAD, 0, 0, { kX86Mov32MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov32MR", "[!0r+!1d],!2r" }, { kX86Mov32AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov32AR", "[!0r+!1r<<!2d+!3d],!4r" }, - { kX86Movnti32MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0F, 0, 0xC3, 0, 0, 0, 0, 0, false }, "Movnti32MR", "[!0r+!1d],!2r" }, - { kX86Movnti32AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0F, 0, 0xC3, 0, 0, 0, 0, 0, false }, "Movnti32AR", "[!0r+!1r<<!2d+!3d],!4r" }, + { kX86Movnti32MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x0F, 0xC3, 0, 0, 0, 0, false }, "Movnti32MR", "[!0r+!1d],!2r" }, + { kX86Movnti32AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x0F, 0xC3, 0, 0, 0, 0, false }, "Movnti32AR", "[!0r+!1r<<!2d+!3d],!4r" }, { kX86Mov32TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov32TR", "fs:[!0d],!1r" }, { kX86Mov32RR, kRegReg, IS_MOVE | IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RR", "!0r,!1r" }, { kX86Mov32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RM", "!0r,[!1r+!2d]" }, @@ -206,8 +206,8 @@ ENCODING_MAP(Cmp, IS_LOAD, 0, 0, { kX86Mov64MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { REX_W, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov64MR", "[!0r+!1d],!2r" }, { kX86Mov64AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { REX_W, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov64AR", "[!0r+!1r<<!2d+!3d],!4r" }, - { kX86Movnti64MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0F, 0, 0xC3, 0, 0, 0, 0, 0, false }, "Movnti64MR", "[!0r+!1d],!2r" }, - { kX86Movnti64AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0F, 0, 0xC3, 0, 0, 0, 0, 0, false }, "Movnti64AR", "[!0r+!1r<<!2d+!3d],!4r" }, + { kX86Movnti64MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { REX_W, 0, 0x0F, 0xC3, 0, 0, 0, 0, false }, "Movnti64MR", "[!0r+!1d],!2r" }, + { kX86Movnti64AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { REX_W, 0, 0x0F, 0xC3, 0, 0, 0, 0, false }, "Movnti64AR", "[!0r+!1r<<!2d+!3d],!4r" }, { kX86Mov64TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, REX_W, 0x89, 0, 0, 0, 0, 0, false }, "Mov64TR", "fs:[!0d],!1r" }, { kX86Mov64RR, kRegReg, IS_MOVE | IS_BINARY_OP | REG_DEF0_USE1, { REX_W, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RR", "!0r,!1r" }, { kX86Mov64RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { REX_W, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RM", "!0r,[!1r+!2d]" }, @@ -917,22 +917,22 @@ void X86Mir2Lir::EmitPrefix(const X86EncodingMap* entry, if (r8_form) { // Do we need an empty REX prefix to normalize byte register addressing? if (RegStorage::RegNum(raw_reg_r) >= 4 && !IsByteSecondOperand(entry)) { - rex |= 0x40; // REX.0000 + rex |= REX; // REX.0000 } else if (modrm_is_reg_reg && RegStorage::RegNum(raw_reg_b) >= 4) { - rex |= 0x40; // REX.0000 + rex |= REX; // REX.0000 } } if (w) { - rex |= 0x48; // REX.W000 + rex |= REX_W; // REX.W000 } if (r) { - rex |= 0x44; // REX.0R00 + rex |= REX_R; // REX.0R00 } if (x) { - rex |= 0x42; // REX.00X0 + rex |= REX_X; // REX.00X0 } if (b) { - rex |= 0x41; // REX.000B + rex |= REX_B; // REX.000B } if (entry->skeleton.prefix1 != 0) { if (cu_->target64 && entry->skeleton.prefix1 == THREAD_PREFIX) { |