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authorSerguei Katkov <serguei.i.katkov@intel.com>2015-04-08 13:26:09 +0600
committerSerguei Katkov <serguei.i.katkov@intel.com>2015-04-10 14:50:43 +0600
commit55501ce0db57bccfa23b0226faffc964203701f9 (patch)
treeb9abd5dcbfd1ec5aff448e4a5d0ce051b27f0466 /compiler/optimizing/code_generator_x86.cc
parent1576be32be4a99a1cffdaaf209a3cd67e8b2f88a (diff)
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Optimizing x86: Fix VisitArraySet for FP value
Instruction generator expects to see FP value in XMM register, so update location builder to follow this. Change-Id: Idca4bb5cdb59249c77fcc6f76cdfcaba47222b3d Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Diffstat (limited to 'compiler/optimizing/code_generator_x86.cc')
-rw-r--r--compiler/optimizing/code_generator_x86.cc8
1 files changed, 7 insertions, 1 deletions
diff --git a/compiler/optimizing/code_generator_x86.cc b/compiler/optimizing/code_generator_x86.cc
index 92b62e2..70d02d1 100644
--- a/compiler/optimizing/code_generator_x86.cc
+++ b/compiler/optimizing/code_generator_x86.cc
@@ -3388,7 +3388,13 @@ void LocationsBuilderX86::VisitArraySet(HArraySet* instruction) {
// Ensure the value is in a byte register.
locations->SetInAt(2, Location::ByteRegisterOrConstant(EAX, instruction->InputAt(2)));
} else {
- locations->SetInAt(2, Location::RegisterOrConstant(instruction->InputAt(2)));
+ bool is_fp_type = (value_type == Primitive::kPrimFloat)
+ || (value_type == Primitive::kPrimDouble);
+ if (is_fp_type) {
+ locations->SetInAt(2, Location::RequiresFpuRegister());
+ } else {
+ locations->SetInAt(2, Location::RegisterOrConstant(instruction->InputAt(2)));
+ }
}
// Temporary registers for the write barrier.
if (needs_write_barrier) {