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authorNicolas Geoffray <ngeoffray@google.com>2015-01-21 12:32:32 +0000
committerNicolas Geoffray <ngeoffray@google.com>2015-01-21 18:50:25 +0000
commit988939683c26c0b1c8808fc206add6337319509a (patch)
tree876e94428276547a29c27ccf17509a42dfe7cda1 /compiler/utils/x86_64
parent59add47cabce3735ccd470cd3b5dac8b112e09ab (diff)
downloadart-988939683c26c0b1c8808fc206add6337319509a.zip
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Enable core callee-save on x64.
Will work on other architectures and FP support in other CLs. Change-Id: I8cef0343eedc7202d206f5217fdf0349035f0e4d
Diffstat (limited to 'compiler/utils/x86_64')
-rw-r--r--compiler/utils/x86_64/assembler_x86_64.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/compiler/utils/x86_64/assembler_x86_64.h b/compiler/utils/x86_64/assembler_x86_64.h
index e24fa1b..2fc251b 100644
--- a/compiler/utils/x86_64/assembler_x86_64.h
+++ b/compiler/utils/x86_64/assembler_x86_64.h
@@ -180,18 +180,18 @@ class Address : public Operand {
void Init(CpuRegister base_in, int32_t disp) {
if (disp == 0 && base_in.LowBits() != RBP) {
SetModRM(0, base_in);
- if (base_in.AsRegister() == RSP) {
+ if (base_in.LowBits() == RSP) {
SetSIB(TIMES_1, CpuRegister(RSP), base_in);
}
} else if (disp >= -128 && disp <= 127) {
SetModRM(1, base_in);
- if (base_in.AsRegister() == RSP) {
+ if (base_in.LowBits() == RSP) {
SetSIB(TIMES_1, CpuRegister(RSP), base_in);
}
SetDisp8(disp);
} else {
SetModRM(2, base_in);
- if (base_in.AsRegister() == RSP) {
+ if (base_in.LowBits() == RSP) {
SetSIB(TIMES_1, CpuRegister(RSP), base_in);
}
SetDisp32(disp);