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author | Zheng Xu <zheng.xu@arm.com> | 2014-06-17 18:17:31 +0800 |
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committer | Zheng Xu <zheng.xu@arm.com> | 2014-06-18 17:53:30 +0800 |
commit | 7c1c263f3227169e055200cc481c022f1cf37213 (patch) | |
tree | 6853f6693728a96287bbcae538b4521338ab1982 /compiler | |
parent | ad6a328506e30b7feb8ddfd2867dec7633a3e52b (diff) | |
download | art-7c1c263f3227169e055200cc481c022f1cf37213.zip art-7c1c263f3227169e055200cc481c022f1cf37213.tar.gz art-7c1c263f3227169e055200cc481c022f1cf37213.tar.bz2 |
AArch64: Fix OpCmpMemImmBranch.
The temp register can be 64-bit in some cases(ArgReg or RefReg).
Always compare 32-bit value no matter what the temp register is.
Change-Id: Ib237dd081da0b5900b8c2418df1621d3245cb03d
Diffstat (limited to 'compiler')
-rw-r--r-- | compiler/dex/quick/arm64/codegen_arm64.h | 4 | ||||
-rw-r--r-- | compiler/dex/quick/arm64/int_arm64.cc | 13 |
2 files changed, 16 insertions, 1 deletions
diff --git a/compiler/dex/quick/arm64/codegen_arm64.h b/compiler/dex/quick/arm64/codegen_arm64.h index b1b83f0..0fa7f2b 100644 --- a/compiler/dex/quick/arm64/codegen_arm64.h +++ b/compiler/dex/quick/arm64/codegen_arm64.h @@ -87,7 +87,9 @@ class Arm64Mir2Lir : public Mir2Lir { OpSize size) OVERRIDE; LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, RegStorage r_src, OpSize size) OVERRIDE; - void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg); + void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) OVERRIDE; + LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, + int offset, int check_value, LIR* target) OVERRIDE; // Required for target - register utilities. RegStorage TargetReg(SpecialTargetRegister reg); diff --git a/compiler/dex/quick/arm64/int_arm64.cc b/compiler/dex/quick/arm64/int_arm64.cc index 2c6b11d..2ac4adb 100644 --- a/compiler/dex/quick/arm64/int_arm64.cc +++ b/compiler/dex/quick/arm64/int_arm64.cc @@ -160,6 +160,19 @@ LIR* Arm64Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_ return branch; } +LIR* Arm64Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, + RegStorage base_reg, int offset, int check_value, + LIR* target) { + // It is possible that temp register is 64-bit. (ArgReg or RefReg) + // Always compare 32-bit value no matter what temp_reg is. + if (temp_reg.Is64Bit()) { + temp_reg = As32BitReg(temp_reg); + } + Load32Disp(base_reg, offset, temp_reg); + LIR* branch = OpCmpImmBranch(cond, temp_reg, check_value, target); + return branch; +} + LIR* Arm64Mir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { bool dest_is_fp = r_dest.IsFloat(); bool src_is_fp = r_src.IsFloat(); |