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authorAndreas Gampe <agampe@google.com>2015-07-08 20:12:25 +0000
committerAndroid (Google) Code Review <android-gerrit@google.com>2015-07-08 20:12:25 +0000
commitfd6fe84c68fdc2ae5f9a1a1bbde80ece4ca557d5 (patch)
tree19e8d3535bceaed97ad957f71e1b033d09ae523f /compiler
parentdb05e31018ef4d1b46a43924b370f061c5457626 (diff)
parenta0b23bbed9b2199e85da401e3b2d0ddef74cd9fb (diff)
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Merge "ART: Release inputs in Long.reverse intrinsic in x86" into mnc-dev
Diffstat (limited to 'compiler')
-rwxr-xr-xcompiler/dex/quick/x86/int_x86.cc15
1 files changed, 15 insertions, 0 deletions
diff --git a/compiler/dex/quick/x86/int_x86.cc b/compiler/dex/quick/x86/int_x86.cc
index d993d93..d1fe167 100755
--- a/compiler/dex/quick/x86/int_x86.cc
+++ b/compiler/dex/quick/x86/int_x86.cc
@@ -1336,9 +1336,24 @@ bool X86Mir2Lir::GenInlinedReverseBits(CallInfo* info, OpSize size) {
}
OpRegReg(kOpRev, rl_result.reg.GetLow(), rl_i.reg.GetHigh());
OpRegReg(kOpRev, rl_result.reg.GetHigh(), r_i_low);
+ // Free up at least one input register if it was a temp. Otherwise we may be in the bad
+ // situation of not having a temp available for SwapBits. Make sure it's not overlapping
+ // with the output, though.
if (rl_i.reg.GetLowReg() == rl_result.reg.GetLowReg()) {
+ // There's definitely a free temp after this.
FreeTemp(r_i_low);
+ } else {
+ // We opportunistically release both here. That saves duplication of the register state
+ // lookup (to see if it's actually a temp).
+ if (rl_i.reg.GetLowReg() != rl_result.reg.GetHighReg()) {
+ FreeTemp(rl_i.reg.GetLow());
+ }
+ if (rl_i.reg.GetHighReg() != rl_result.reg.GetLowReg() &&
+ rl_i.reg.GetHighReg() != rl_result.reg.GetHighReg()) {
+ FreeTemp(rl_i.reg.GetHigh());
+ }
}
+
SwapBits(rl_result.reg.GetLow(), 1, 0x55555555);
SwapBits(rl_result.reg.GetLow(), 2, 0x33333333);
SwapBits(rl_result.reg.GetLow(), 4, 0x0f0f0f0f);