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| author | Mark Mendell <mark.p.mendell@intel.com> | 2014-06-06 15:19:45 -0400 |
|---|---|---|
| committer | Ian Rogers <irogers@google.com> | 2014-06-08 22:27:11 -0700 |
| commit | 33ecf8d692eb192aa0ddb752d3ffe1e899e0f42e (patch) | |
| tree | bf29fe047b99ff3e387c1eff5c2ea2215bdfda16 /disassembler | |
| parent | 6473c0ab5fe81761c34515c5049d8baf8ee1d35e (diff) | |
| download | art-33ecf8d692eb192aa0ddb752d3ffe1e899e0f42e.zip art-33ecf8d692eb192aa0ddb752d3ffe1e899e0f42e.tar.gz art-33ecf8d692eb192aa0ddb752d3ffe1e899e0f42e.tar.bz2 | |
Add Move with Sign Extend Double to disassembler
I noticed another missing instruction.
Change-Id: I71170496b014ac2609116eff2aeb13a13e71e263
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
Diffstat (limited to 'disassembler')
| -rw-r--r-- | disassembler/disassembler_x86.cc | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/disassembler/disassembler_x86.cc b/disassembler/disassembler_x86.cc index 456e3b5..e6a6860 100644 --- a/disassembler/disassembler_x86.cc +++ b/disassembler/disassembler_x86.cc @@ -258,6 +258,17 @@ DISASSEMBLER_ENTRY(cmp, reg_in_opcode = true; target_specific = true; break; + case 0x63: + if (rex == 0x48) { + opcode << "movsxd"; + has_modrm = true; + load = true; + } else { + // In 32-bit mode (!supports_rex_) this is ARPL, with no REX prefix the functionality is the + // same as 'mov' but the use of the instruction is discouraged. + opcode << StringPrintf("unknown opcode '%02X'", *instr); + } + break; case 0x68: opcode << "push"; immediate_bytes = 4; break; case 0x69: opcode << "imul"; load = true; has_modrm = true; immediate_bytes = 4; break; case 0x6A: opcode << "push"; immediate_bytes = 1; break; |