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| author | Ningsheng Jian <ningsheng.jian@arm.com> | 2014-11-25 16:48:07 +0800 |
|---|---|---|
| committer | Ningsheng Jian <ningsheng.jian@arm.com> | 2014-12-11 09:08:22 +0800 |
| commit | a262f7707330dccfb50af6345813083182b61043 (patch) | |
| tree | a8ab4e42654f47c9deea517f6c4e2020c62d5724 /disassembler | |
| parent | 3e465bec65067ebfdf662469cf85dd82cd077bdd (diff) | |
| download | art-a262f7707330dccfb50af6345813083182b61043.zip art-a262f7707330dccfb50af6345813083182b61043.tar.gz art-a262f7707330dccfb50af6345813083182b61043.tar.bz2 | |
ARM: Combine multiply accumulate operations.
Try to combine integer multiply and add(sub) into a MAC operation.
For AArch64, also try to combine long type multiply and add(sub).
Change-Id: Ic85812e941eb5a66abc355cab81a4dd16de1b66e
Diffstat (limited to 'disassembler')
| -rw-r--r-- | disassembler/disassembler_arm.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/disassembler/disassembler_arm.cc b/disassembler/disassembler_arm.cc index 9243b1a..52fd736 100644 --- a/disassembler/disassembler_arm.cc +++ b/disassembler/disassembler_arm.cc @@ -1498,7 +1498,7 @@ size_t DisassemblerArm::DumpThumb32(std::ostream& os, const uint8_t* instr_ptr) } else if ((op2 >> 3) == 6) { // 0110xxx // Multiply, multiply accumulate, and absolute difference op1 = (instr >> 20) & 0x7; - op2 = (instr >> 4) & 0x2; + op2 = (instr >> 4) & 0x1; ArmRegister Ra(instr, 12); ArmRegister Rn(instr, 16); ArmRegister Rm(instr, 0); |