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authorJean Christophe Beyler <jean.christophe.beyler@intel.com>2014-07-25 12:32:18 -0700
committerChao-ying Fu <chao-ying.fu@intel.com>2014-08-26 11:38:04 -0700
commitb5bce7cc9f1130ab4932ba8e6917c362bf871f24 (patch)
tree45d3b064227213da49d047c3c718e23f33b47cad /disassembler
parent3b6711faf7b0b10eaa6c48ba854160bcecd00166 (diff)
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ART: Add non-temporal store support
Added non-temporal store support as a hint from the ME. Added the implementation of the memory barrier extended instruction that supports non-temporal stores by explicitly serializing all previous store-to-memory instructions. Change-Id: I8205a92083f9725253d8ce893671a133a0b6849d Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com> Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
Diffstat (limited to 'disassembler')
-rw-r--r--disassembler/disassembler_x86.cc1
1 files changed, 1 insertions, 0 deletions
diff --git a/disassembler/disassembler_x86.cc b/disassembler/disassembler_x86.cc
index 0bf758e..7551add 100644
--- a/disassembler/disassembler_x86.cc
+++ b/disassembler/disassembler_x86.cc
@@ -764,6 +764,7 @@ DISASSEMBLER_ENTRY(cmp,
case 0xB7: opcode << "movzxw"; has_modrm = true; load = true; break;
case 0xBE: opcode << "movsxb"; has_modrm = true; load = true; byte_second_operand = true; rex |= (rex == 0 ? 0 : 0b1000); break;
case 0xBF: opcode << "movsxw"; has_modrm = true; load = true; break;
+ case 0xC3: opcode << "movnti"; store = true; has_modrm = true; break;
case 0xC5:
if (prefix[2] == 0x66) {
opcode << "pextrw";