ART: Enable the use of relative addresses in the arm64 disassembler.

Also, only keep register aliases for the link register 'lr' and the
thread register 'tr' in the arm64 disassembler. Other aliases are not
very important, and this way we don't have to provide aliases
specialised for Quick or Optimizing.

Change-Id: Ie7a04910f0c587710a0cf2648203d7e89eab5d1f

2 files changed, 16 insertions, 24 deletions

diff --git a/disassembler/disassembler_arm64.cc b/disassembler/disassembler_arm64.cc
index 4ff44b4..d195efc 100644
--- a/disassembler/disassembler_arm64.cc
+++ b/disassembler/disassembler_arm64.cc
@@ -43,18 +43,15 @@ void CustomDisassembler::AppendRegisterNameToOutput(
     const vixl::Instruction* instr,
     const vixl::CPURegister& reg) {
   USE(instr);
-  if (reg.IsRegister()) {
-    switch (reg.code()) {
-      case IP0: AppendToOutput(reg.Is64Bits() ? "ip0" : "wip0"); return;
-      case IP1: AppendToOutput(reg.Is64Bits() ? "ip1" : "wip1"); return;
-      case TR:  AppendToOutput(reg.Is64Bits() ? "tr"  :  "w18"); return;
-      case ETR: AppendToOutput(reg.Is64Bits() ? "etr" :  "w21"); return;
-      case FP:  AppendToOutput(reg.Is64Bits() ? "fp"  :  "w29"); return;
-      case LR:  AppendToOutput(reg.Is64Bits() ? "lr"  :  "w30"); return;
-      default:
-        // Fall through.
-        break;
+  if (reg.IsRegister() && reg.Is64Bits()) {
+    if (reg.code() == TR) {
+      AppendToOutput("tr");
+      return;
+    } else if (reg.code() == LR) {
+      AppendToOutput("lr");
+      return;
     }
+    // Fall through.
   }
   // Print other register names as usual.
   Disassembler::AppendRegisterNameToOutput(instr, reg);
@@ -105,13 +102,7 @@ void CustomDisassembler::VisitLoadStoreUnsignedOffset(const vixl::Instruction* i
 size_t DisassemblerArm64::Dump(std::ostream& os, const uint8_t* begin) {
   const vixl::Instruction* instr = reinterpret_cast<const vixl::Instruction*>(begin);
   decoder.Decode(instr);
-  // TODO: Use FormatInstructionPointer() once VIXL provides the appropriate
-  // features.
-  // VIXL does not yet allow remapping addresses disassembled. Using
-  // FormatInstructionPointer() would show incoherences between the instruction
-  // location addresses and the target addresses disassembled by VIXL (eg. for
-  // branch instructions).
-  os << StringPrintf("%p", instr)
+    os << FormatInstructionPointer(begin)
      << StringPrintf(": %08x\t%s\n", instr->InstructionBits(), disasm.GetOutput());
   return vixl::kInstructionSize;
 }
diff --git a/disassembler/disassembler_arm64.h b/disassembler/disassembler_arm64.h
index 57f11c8..3fb5c7f 100644
--- a/disassembler/disassembler_arm64.h
+++ b/disassembler/disassembler_arm64.h
@@ -30,8 +30,12 @@ namespace arm64 {
 
 class CustomDisassembler FINAL : public vixl::Disassembler {
  public:
-  explicit CustomDisassembler(bool read_literals) :
-      vixl::Disassembler(), read_literals_(read_literals) {}
+  explicit CustomDisassembler(DisassemblerOptions* options) :
+      vixl::Disassembler(), read_literals_(options->can_read_literals_) {
+    if (!options->absolute_addresses_) {
+      MapCodeAddress(0, reinterpret_cast<const vixl::Instruction*>(options->base_address_));
+    }
+  }
 
   // Use register aliases in the disassembly.
   void AppendRegisterNameToOutput(const vixl::Instruction* instr,
@@ -55,11 +59,8 @@ class CustomDisassembler FINAL : public vixl::Disassembler {
 
 class DisassemblerArm64 FINAL : public Disassembler {
  public:
-  // TODO: Update this code once VIXL provides the ability to map code addresses
-  // to disassemble as a different address (the way FormatInstructionPointer()
-  // does).
   explicit DisassemblerArm64(DisassemblerOptions* options) :
-      Disassembler(options), disasm(options->can_read_literals_) {
+      Disassembler(options), disasm(options) {
     decoder.AppendVisitor(&disasm);
   }