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authorAlexei Zavjalov <alexei.zavjalov@intel.com>2014-05-15 16:02:46 +0700
committerAndreas Gampe <agampe@google.com>2014-06-10 10:01:01 -0700
commit41c507a9dae44b8329a857da3d9810fab2e9ddc6 (patch)
tree78d2a1f81227ca41c4541be5fd87cacabaf06ed2 /runtime/globals.h
parentf71f8da2e83fefcec42ad77385c1df62f521ddad (diff)
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ART: Generalize code to find PC for artInvokeInterfaceTrampoline
This allows to determine target method when the interface method has no dex index, now also for X86-64 and ARM64. Add constexpr functions to callee_save_frame.h to have compile-time sizes of callee-save frames. Add a test that ensures they agree with computations by the corresponding ArtMethod methods. Move some instruction-set functions into the header file to allow inlining them. Move arch-specific pointer sizes and alignment sizes out of globals.h to instruction_set.h to reduce dependencies. Change-Id: I2997592c7dd1f4dd2bd497522c64bd235ae615a6 Signed-off-by: Alexei Zavjalov <alexei.zavjalov@intel.com>
Diffstat (limited to 'runtime/globals.h')
-rw-r--r--runtime/globals.h21
1 files changed, 0 insertions, 21 deletions
diff --git a/runtime/globals.h b/runtime/globals.h
index 07fadb9..58c2118 100644
--- a/runtime/globals.h
+++ b/runtime/globals.h
@@ -36,13 +36,6 @@ static constexpr size_t GB = KB * KB * KB;
static constexpr size_t kWordSize = sizeof(word);
static constexpr size_t kPointerSize = sizeof(void*);
-// Architecture-specific pointer sizes
-static constexpr size_t kArmPointerSize = 4;
-static constexpr size_t kArm64PointerSize = 8;
-static constexpr size_t kMipsPointerSize = 4;
-static constexpr size_t kX86PointerSize = 4;
-static constexpr size_t kX86_64PointerSize = 8;
-
static constexpr size_t kBitsPerByte = 8;
static constexpr size_t kBitsPerByteLog2 = 3;
static constexpr int kBitsPerWord = kWordSize * kBitsPerByte;
@@ -51,20 +44,6 @@ static constexpr size_t kWordHighBitMask = static_cast<size_t>(1) << (kBitsPerWo
// Required stack alignment
static constexpr size_t kStackAlignment = 16;
-// ARM instruction alignment. ARM processors require code to be 4-byte aligned,
-// but ARM ELF requires 8..
-static constexpr size_t kArmAlignment = 8;
-
-// ARM64 instruction alignment. This is the recommended alignment for maximum performance.
-static constexpr size_t kArm64Alignment = 16;
-
-// MIPS instruction alignment. MIPS processors require code to be 4-byte aligned.
-// TODO: Can this be 4?
-static constexpr size_t kMipsAlignment = 8;
-
-// X86 instruction alignment. This is the recommended alignment for maximum performance.
-static constexpr size_t kX86Alignment = 16;
-
// System page size. We check this against sysconf(_SC_PAGE_SIZE) at runtime, but use a simple
// compile-time constant so the compiler can generate better code.
static constexpr int kPageSize = 4096;