More target-independence

Continuing to move target-specific code from the Arm
code generator into the independent realm.  This will be
done in multiple small steps.

In this CL, the focus is on unifying the LIR data structure and
various enums that don't really need to be target specific. Also
creates two new shared source files: GenCommon.cc (to hold
top-level code generation functions) and GenInvoke.cc (which
is likely to be shared only by the Arm and Mips targets).

Also added is a makefile hack to build for Mips (which we'll
eventually remove when the compiler support multiple targets
via the command line) and various minor cleanups.

Overall, this CL moves more than 3,000 lines of code from
target dependent to target independent.

Change-Id: I431ca4ae728100ed7d0e9d83a966a3f789f731b1

11 files changed, 369 insertions, 315 deletions

diff --git a/src/compiler/codegen/mips/ArchFactory.cc b/src/compiler/codegen/mips/ArchFactory.cc
index 6a3e667..cb9645d 100644
--- a/src/compiler/codegen/mips/ArchFactory.cc
+++ b/src/compiler/codegen/mips/ArchFactory.cc
@@ -39,20 +39,6 @@ namespace art {
 
 STATIC void genDebuggerUpdate(CompilationUnit* cUnit, int32_t offset);
 
-/* Generate conditional branch instructions */
-STATIC MipsLIR* genConditionalBranch(CompilationUnit* cUnit,
-                                    MipsConditionCode cond,
-                                    MipsLIR* target)
-{
-    UNIMPLEMENTED(FATAL) << "Needs mips version";
-    return NULL;
-#if 0
-    MipsLIR* branch = opCondBranch(cUnit, cond);
-    branch->generic.target = (LIR*) target;
-    return branch;
-#endif
-}
-
 /* Generate unconditional branch instructions */
 STATIC MipsLIR* genUnconditionalBranch(CompilationUnit* cUnit, MipsLIR* target)
 {
@@ -72,22 +58,19 @@ STATIC MipsLIR* callRuntimeHelper(CompilationUnit* cUnit, int reg)
  */
 STATIC void markGCCard(CompilationUnit* cUnit, int valReg, int tgtAddrReg)
 {
-    UNIMPLEMENTED(FATAL) << "Needs mips version";
-#if 0
     int regCardBase = oatAllocTemp(cUnit);
     int regCardNo = oatAllocTemp(cUnit);
-    MipsLIR* branchOver = genCmpImmBranch(cUnit, kMipsCondEq, valReg, 0);
+    MipsLIR* branchOver = opCompareBranchCC(cUnit, kMipsCondEq, valReg, r_ZERO);
     loadWordDisp(cUnit, rSELF, Thread::CardTableOffset().Int32Value(),
                  regCardBase);
     opRegRegImm(cUnit, kOpLsr, regCardNo, tgtAddrReg, GC_CARD_SHIFT);
     storeBaseIndexed(cUnit, regCardBase, regCardNo, regCardBase, 0,
                      kUnsignedByte);
-    MipsLIR* target = newLIR0(cUnit, kMipsPseudoTargetLabel);
+    MipsLIR* target = newLIR0(cUnit, kPseudoTargetLabel);
     target->defMask = ENCODE_ALL;
     branchOver->generic.target = (LIR*)target;
     oatFreeTemp(cUnit, regCardBase);
     oatFreeTemp(cUnit, regCardNo);
-#endif
 }
 
 /*
@@ -97,14 +80,11 @@ STATIC void markGCCard(CompilationUnit* cUnit, int valReg, int tgtAddrReg)
  */
 STATIC void loadCurrMethodDirect(CompilationUnit *cUnit, int rTgt)
 {
-    UNIMPLEMENTED(FATAL) << "Needs mips version";
-#if 0
 #if defined(METHOD_IN_REG)
     genRegCopy(cUnit, rTgt, rMETHOD);
 #else
     loadWordDisp(cUnit, rSP, 0, rTgt);
 #endif
-#endif
 }
 
 STATIC int loadCurrMethod(CompilationUnit *cUnit)
@@ -118,70 +98,49 @@ STATIC int loadCurrMethod(CompilationUnit *cUnit)
 #endif
 }
 
-STATIC MipsLIR* genCheck(CompilationUnit* cUnit, MipsConditionCode cCode,
-                        MIR* mir, MipsThrowKind kind)
-{
-    UNIMPLEMENTED(FATAL) << "Needs mips version";
-    return 0;
-#if 0
-    MipsLIR* tgt = (MipsLIR*)oatNew(cUnit, sizeof(MipsLIR), true, kAllocLIR);
-    tgt->opcode = kMipsPseudoThrowTarget;
-    tgt->operands[0] = kind;
-    tgt->operands[1] = mir ? mir->offset : 0;
-    MipsLIR* branch = genConditionalBranch(cUnit, cCode, tgt);
-    // Remember branch target - will process later
-    oatInsertGrowableList(cUnit, &cUnit->throwLaunchpads, (intptr_t)tgt);
-    return branch;
-#endif
-}
-
 STATIC MipsLIR* genImmedCheck(CompilationUnit* cUnit, MipsConditionCode cCode,
                              int reg, int immVal, MIR* mir, MipsThrowKind kind)
 {
-    UNIMPLEMENTED(FATAL) << "Needs mips version";
-    return 0;
-#if 0
     MipsLIR* tgt = (MipsLIR*)oatNew(cUnit, sizeof(MipsLIR), true, kAllocLIR);
-    tgt->opcode = kMipsPseudoThrowTarget;
+    tgt->opcode = kPseudoThrowTarget;
     tgt->operands[0] = kind;
     tgt->operands[1] = mir->offset;
     MipsLIR* branch;
     if (cCode == kMipsCondAl) {
         branch = genUnconditionalBranch(cUnit, tgt);
     } else {
-        branch = genCmpImmBranch(cUnit, cCode, reg, immVal);
+        int tReg;
+        if (immVal == 0) {
+            tReg = r_ZERO;
+        } else {
+            tReg = oatAllocTemp(cUnit);
+            loadConstant(cUnit, tReg, immVal);
+        }
+        branch = opCompareBranchCC(cUnit, cCode, reg, tReg);
         branch->generic.target = (LIR*)tgt;
     }
     // Remember branch target - will process later
     oatInsertGrowableList(cUnit, &cUnit->throwLaunchpads, (intptr_t)tgt);
     return branch;
-#endif
 }
 
 /* Perform null-check on a register.  */
 STATIC MipsLIR* genNullCheck(CompilationUnit* cUnit, int sReg, int mReg,
                              MIR* mir)
 {
-    UNIMPLEMENTED(FATAL) << "Needs mips version";
-    return 0;
-#if 0
     if (!(cUnit->disableOpt & (1 << kNullCheckElimination)) &&
         mir->optimizationFlags & MIR_IGNORE_NULL_CHECK) {
         return NULL;
     }
     return genImmedCheck(cUnit, kMipsCondEq, mReg, 0, mir, kMipsThrowNullPointer);
-#endif
 }
 
 /* Perform check on two registers */
 STATIC TGT_LIR* genRegRegCheck(CompilationUnit* cUnit, MipsConditionCode cCode,
                                int reg1, int reg2, MIR* mir, MipsThrowKind kind)
 {
-    UNIMPLEMENTED(FATAL) << "Needs mips version";
-    return 0;
-#if 0
     MipsLIR* tgt = (MipsLIR*)oatNew(cUnit, sizeof(MipsLIR), true, kAllocLIR);
-    tgt->opcode = kMipsPseudoThrowTarget;
+    tgt->opcode = kPseudoThrowTarget;
     tgt->operands[0] = kind;
     tgt->operands[1] = mir ? mir->offset : 0;
     tgt->operands[2] = reg1;
@@ -191,7 +150,6 @@ STATIC TGT_LIR* genRegRegCheck(CompilationUnit* cUnit, MipsConditionCode cCode,
     // Remember branch target - will process later
     oatInsertGrowableList(cUnit, &cUnit->throwLaunchpads, (intptr_t)tgt);
     return branch;
-#endif
 }
 
 /*
@@ -202,27 +160,26 @@ STATIC TGT_LIR* genRegRegCheck(CompilationUnit* cUnit, MipsConditionCode cCode,
 STATIC void genNewArray(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
                         RegLocation rlSrc)
 {
-    UNIMPLEMENTED(FATAL) << "Needs mips version";
-#if 0
     oatFlushAllRegs(cUnit);    /* Everything to home location */
+    oatLockCallTemps(cUnit);
+    int addrReg = oatAllocTemp(cUnit);
     uint32_t type_idx = mir->dalvikInsn.vC;
     if (cUnit->compiler->CanAccessTypeWithoutChecks(cUnit->method_idx,
                                                     cUnit->dex_cache,
                                                     *cUnit->dex_file,
                                                     type_idx)) {
         loadWordDisp(cUnit, rSELF,
-                     OFFSETOF_MEMBER(Thread, pAllocArrayFromCode), rLR);
+                     OFFSETOF_MEMBER(Thread, pAllocArrayFromCode), addrReg);
     } else {
         loadWordDisp(cUnit, rSELF,
-                     OFFSETOF_MEMBER(Thread, pAllocArrayFromCodeWithAccessCheck), rLR);
+                     OFFSETOF_MEMBER(Thread, pAllocArrayFromCodeWithAccessCheck), addrReg);
     }
-    loadCurrMethodDirect(cUnit, r1);              // arg1 <- Method*
-    loadConstant(cUnit, r0, type_idx);            // arg0 <- type_id
-    loadValueDirectFixed(cUnit, rlSrc, r2);       // arg2 <- count
-    callRuntimeHelper(cUnit, rLR);
+    loadCurrMethodDirect(cUnit, r_ARG1);              // arg1 <- Method*
+    loadConstant(cUnit, r_ARG0, type_idx);            // arg0 <- type_id
+    loadValueDirectFixed(cUnit, rlSrc, r_ARG2);       // arg2 <- count
+    callRuntimeHelper(cUnit, addrReg);
     RegLocation rlResult = oatGetReturn(cUnit);
     storeValue(cUnit, rlDest, rlResult);
-#endif
 }
 
 /*
@@ -233,34 +190,36 @@ STATIC void genNewArray(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
  */
 STATIC void genFilledNewArray(CompilationUnit* cUnit, MIR* mir, bool isRange)
 {
-    UNIMPLEMENTED(FATAL) << "Needs mips version";
-#if 0
     DecodedInstruction* dInsn = &mir->dalvikInsn;
     int elems = dInsn->vA;
     int typeId = dInsn->vB;
     oatFlushAllRegs(cUnit);    /* Everything to home location */
+    oatLockCallTemps(cUnit);
+    int addrReg = oatAllocTemp(cUnit);
     if (cUnit->compiler->CanAccessTypeWithoutChecks(cUnit->method_idx,
                                                     cUnit->dex_cache,
                                                     *cUnit->dex_file,
                                                     typeId)) {
         loadWordDisp(cUnit, rSELF,
-                     OFFSETOF_MEMBER(Thread, pCheckAndAllocArrayFromCode), rLR);
+                     OFFSETOF_MEMBER(Thread, pCheckAndAllocArrayFromCode),
+                                     addrReg);
     } else {
         loadWordDisp(cUnit, rSELF,
-                     OFFSETOF_MEMBER(Thread, pCheckAndAllocArrayFromCodeWithAccessCheck), rLR);
+                     OFFSETOF_MEMBER(Thread,
+                     pCheckAndAllocArrayFromCodeWithAccessCheck), addrReg);
     }
-    loadCurrMethodDirect(cUnit, r1);              // arg1 <- Method*
-    loadConstant(cUnit, r0, typeId);              // arg0 <- type_id
-    loadConstant(cUnit, r2, elems);               // arg2 <- count
-    callRuntimeHelper(cUnit, rLR);
+    loadCurrMethodDirect(cUnit, r_ARG1);              // arg1 <- Method*
+    loadConstant(cUnit, r_ARG0, typeId);              // arg0 <- type_id
+    loadConstant(cUnit, r_ARG2, elems);               // arg2 <- count
+    callRuntimeHelper(cUnit, addrReg);
     /*
      * NOTE: the implicit target for OP_FILLED_NEW_ARRAY is the
      * return region.  Because AllocFromCode placed the new array
-     * in r0, we'll just lock it into place.  When debugger support is
+     * in r_V0, we'll just lock it into place.  When debugger support is
      * added, it may be necessary to additionally copy all return
      * values to a home location in thread-local storage
      */
-    oatLockTemp(cUnit, r0);
+    oatLockTemp(cUnit, r_V0);
 
     // Having a range of 0 is legal
     if (isRange && (dInsn->vA > 0)) {
@@ -288,32 +247,31 @@ STATIC void genFilledNewArray(CompilationUnit* cUnit, MIR* mir, bool isRange)
         int rSrc = oatAllocTemp(cUnit);
         int rDst = oatAllocTemp(cUnit);
         int rIdx = oatAllocTemp(cUnit);
-        int rVal = rLR;  // Using a lot of temps, rLR is known free here
+        int rVal = oatAllocTemp(cUnit);
         // Set up source pointer
         RegLocation rlFirst = oatGetSrc(cUnit, mir, 0);
         opRegRegImm(cUnit, kOpAdd, rSrc, rSP,
                     oatSRegOffset(cUnit, rlFirst.sRegLow));
         // Set up the target pointer
-        opRegRegImm(cUnit, kOpAdd, rDst, r0,
+        opRegRegImm(cUnit, kOpAdd, rDst, r_V0,
                     Array::DataOffset().Int32Value());
         // Set up the loop counter (known to be > 0)
         loadConstant(cUnit, rIdx, dInsn->vA - 1);
         // Generate the copy loop.  Going backwards for convenience
-        MipsLIR* target = newLIR0(cUnit, kMipsPseudoTargetLabel);
+        MipsLIR* target = newLIR0(cUnit, kPseudoTargetLabel);
         target->defMask = ENCODE_ALL;
         // Copy next element
         loadBaseIndexed(cUnit, rSrc, rIdx, rVal, 2, kWord);
         storeBaseIndexed(cUnit, rDst, rIdx, rVal, 2, kWord);
-        // Use setflags encoding here
-        newLIR3(cUnit, kThumb2SubsRRI12, rIdx, rIdx, 1);
-        MipsLIR* branch = opCondBranch(cUnit, kMipsCondGe);
+        opRegImm(cUnit, kOpSub, rIdx, 1);
+        MipsLIR* branch = opCompareBranchCC(cUnit, kMipsCondGe, rIdx, r_ZERO);
         branch->generic.target = (LIR*)target;
     } else if (!isRange) {
         // TUNING: interleave
         for (unsigned int i = 0; i < dInsn->vA; i++) {
             RegLocation rlArg = loadValue(cUnit,
                 oatGetSrc(cUnit, mir, i), kCoreReg);
-            storeBaseDisp(cUnit, r0,
+            storeBaseDisp(cUnit, r_V0,
                           Array::DataOffset().Int32Value() +
                           i * 4, rlArg.lowReg, kWord);
             // If the loadValue caused a temp to be allocated, free it
@@ -322,14 +280,11 @@ STATIC void genFilledNewArray(CompilationUnit* cUnit, MIR* mir, bool isRange)
             }
         }
     }
-#endif
 }
 
 STATIC void genSput(CompilationUnit* cUnit, MIR* mir, RegLocation rlSrc,
                     bool isLongOrDouble, bool isObject)
 {
-    UNIMPLEMENTED(FATAL) << "Needs mips version";
-#if 0
     int fieldOffset;
     int ssbIndex;
     bool isVolatile;
@@ -357,6 +312,7 @@ STATIC void genSput(CompilationUnit* cUnit, MIR* mir, RegLocation rlSrc,
             oatFlushAllRegs(cUnit);
             // Using fixed register to sync with possible call to runtime
             // support.
+            oatLockCallTemps(cUnit);
             rMethod = r1;
             oatLockTemp(cUnit, rMethod);
             loadCurrMethodDirect(cUnit, rMethod);
@@ -371,12 +327,13 @@ STATIC void genSput(CompilationUnit* cUnit, MIR* mir, RegLocation rlSrc,
             // rBase now points at appropriate static storage base (Class*)
             // or NULL if not initialized. Check for NULL and call helper if NULL.
             // TUNING: fast path should fall through
-            MipsLIR* branchOver = genCmpImmBranch(cUnit, kMipsCondNe, rBase, 0);
+            MipsLIR* branchOver = opCmpImmBranchCC(cUnit, kMipsCondNe,
+                                                   rBase, 0);
             loadWordDisp(cUnit, rSELF,
                          OFFSETOF_MEMBER(Thread, pInitializeStaticStorage), rLR);
             loadConstant(cUnit, r0, ssbIndex);
             callRuntimeHelper(cUnit, rLR);
-            MipsLIR* skipTarget = newLIR0(cUnit, kMipsPseudoTargetLabel);
+            MipsLIR* skipTarget = newLIR0(cUnit, kPseudoTargetLabel);
             skipTarget->defMask = ENCODE_ALL;
             branchOver->generic.target = (LIR*)skipTarget;
         }
@@ -419,7 +376,6 @@ STATIC void genSput(CompilationUnit* cUnit, MIR* mir, RegLocation rlSrc,
         }
         callRuntimeHelper(cUnit, rLR);
     }
-#endif
 }
 
 STATIC void genSget(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
@@ -468,12 +424,12 @@ STATIC void genSget(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
             // rBase now points at appropriate static storage base (Class*)
             // or NULL if not initialized. Check for NULL and call helper if NULL.
             // TUNING: fast path should fall through
-            MipsLIR* branchOver = genCmpImmBranch(cUnit, kMipsCondNe, rBase, 0);
+            MipsLIR* branchOver = opCmpImmBranchCC(cUnit, kMipsCondNe, rBase, 0);
             loadWordDisp(cUnit, rSELF,
                          OFFSETOF_MEMBER(Thread, pInitializeStaticStorage), rLR);
             loadConstant(cUnit, r0, ssbIndex);
             callRuntimeHelper(cUnit, rLR);
-            MipsLIR* skipTarget = newLIR0(cUnit, kMipsPseudoTargetLabel);
+            MipsLIR* skipTarget = newLIR0(cUnit, kPseudoTargetLabel);
             skipTarget->defMask = ENCODE_ALL;
             branchOver->generic.target = (LIR*)skipTarget;
         }
@@ -947,10 +903,10 @@ STATIC void genShowTarget(CompilationUnit* cUnit)
 {
     UNIMPLEMENTED(FATAL) << "Needs mips version";
 #if 0
-    MipsLIR* branchOver = genCmpImmBranch(cUnit, kMipsCondNe, rLR, 0);
+    MipsLIR* branchOver = opCmpImmBranch(cUnit, kMipsCondNe, rLR, 0);
     loadWordDisp(cUnit, rSELF,
                  OFFSETOF_MEMBER(Thread, pDebugMe), rLR);
-    MipsLIR* target = newLIR0(cUnit, kMipsPseudoTargetLabel);
+    MipsLIR* target = newLIR0(cUnit, kPseudoTargetLabel);
     target->defMask = -1;
     branchOver->generic.target = (LIR*)target;
 #endif
@@ -1164,7 +1120,7 @@ STATIC void genEntrySequence(CompilationUnit* cUnit, BasicBlock* bb)
     bool skipOverflowCheck = ((cUnit->attrs & METHOD_IS_LEAF) &&
                               ((size_t)cUnit->frameSize <
                               Thread::kStackOverflowReservedBytes));
-    newLIR0(cUnit, kMipsPseudoMethodEntry);
+    newLIR0(cUnit, kPseudoMethodEntry);
     if (!skipOverflowCheck) {
         /* Load stack limit */
         loadWordDisp(cUnit, rSELF,
@@ -1220,7 +1176,7 @@ STATIC void genExitSequence(CompilationUnit* cUnit, BasicBlock* bb)
     oatLockTemp(cUnit, r0);
     oatLockTemp(cUnit, r1);
 
-    newLIR0(cUnit, kMipsPseudoMethodExit);
+    newLIR0(cUnit, kPseudoMethodExit);
     /* If we're compiling for the debugger, generate an update callout */
     if (cUnit->genDebugger) {
         genDebuggerUpdate(cUnit, DEBUGGER_METHOD_EXIT);
diff --git a/src/compiler/codegen/mips/ArchUtility.cc b/src/compiler/codegen/mips/ArchUtility.cc
index f218436..2e8d417 100644
--- a/src/compiler/codegen/mips/ArchUtility.cc
+++ b/src/compiler/codegen/mips/ArchUtility.cc
@@ -221,50 +221,50 @@ void oatDumpLIRInsn(CompilationUnit* cUnit, LIR* arg, unsigned char* baseAddr)
 
     /* Handle pseudo-ops individually, and all regular insns as a group */
     switch(lir->opcode) {
-        case kMipsPseudoMethodEntry:
+        case kPseudoMethodEntry:
             LOG(INFO) << "-------- method entry " <<
                 PrettyMethod(cUnit->method_idx, *cUnit->dex_file);
             break;
-        case kMipsPseudoMethodExit:
+        case kPseudoMethodExit:
             LOG(INFO) << "-------- Method_Exit";
             break;
-        case kMipsPseudoBarrier:
+        case kPseudoBarrier:
             LOG(INFO) << "-------- BARRIER";
             break;
-        case kMipsPseudoExtended:
+        case kPseudoExtended:
             LOG(INFO) << "-------- " << (char* ) dest;
             break;
-        case kMipsPseudoSSARep:
+        case kPseudoSSARep:
             DUMP_SSA_REP(LOG(INFO) << "-------- kMirOpPhi: " <<  (char* ) dest);
             break;
-        case kMipsPseudoEntryBlock:
+        case kPseudoEntryBlock:
             LOG(INFO) << "-------- entry offset: 0x" << std::hex << dest;
             break;
-        case kMipsPseudoDalvikByteCodeBoundary:
+        case kPseudoDalvikByteCodeBoundary:
             LOG(INFO) << "-------- dalvik offset: 0x" << std::hex <<
                  lir->generic.dalvikOffset << " @ " << (char* )lir->operands[0];
             break;
-        case kMipsPseudoExitBlock:
+        case kPseudoExitBlock:
             LOG(INFO) << "-------- exit offset: 0x" << std::hex << dest;
             break;
-        case kMipsPseudoPseudoAlign4:
+        case kPseudoPseudoAlign4:
             LOG(INFO) << (intptr_t)baseAddr + offset << " (0x" << std::hex <<
                 offset << "): .align4";
             break;
-        case kMipsPseudoEHBlockLabel:
+        case kPseudoEHBlockLabel:
             LOG(INFO) << "Exception_Handling:";
             break;
-        case kMipsPseudoTargetLabel:
-        case kMipsPseudoNormalBlockLabel:
+        case kPseudoTargetLabel:
+        case kPseudoNormalBlockLabel:
             LOG(INFO) << "L" << (intptr_t)lir << ":";
             break;
-        case kMipsPseudoThrowTarget:
+        case kPseudoThrowTarget:
             LOG(INFO) << "LT" << (intptr_t)lir << ":";
             break;
-        case kMipsPseudoSuspendTarget:
+        case kPseudoSuspendTarget:
             LOG(INFO) << "LS" << (intptr_t)lir << ":";
             break;
-        case kMipsPseudoCaseLabel:
+        case kPseudoCaseLabel:
             LOG(INFO) << "LC" << (intptr_t)lir << ": Case target 0x" <<
                 std::hex << lir->operands[0] << "|" << std::dec <<
                 lir->operands[0];
diff --git a/src/compiler/codegen/mips/Assemble.cc b/src/compiler/codegen/mips/Assemble.cc
index 9e8af2a..5b6e6ed 100644
--- a/src/compiler/codegen/mips/Assemble.cc
+++ b/src/compiler/codegen/mips/Assemble.cc
@@ -540,7 +540,7 @@ int oatAssignInsnOffsets(CompilationUnit* cUnit)
                 mipsLIR->flags.size = EncodingMap[mipsLIR->opcode].size * 2;
                 offset += mipsLIR->flags.size;
             }
-        } else if (mipsLIR->opcode == kMipsPseudoPseudoAlign4) {
+        } else if (mipsLIR->opcode == kPseudoPseudoAlign4) {
             if (offset & 0x2) {
                 offset += 2;
                 mipsLIR->operands[0] = 1;
diff --git a/src/compiler/codegen/mips/CodegenCommon.cc b/src/compiler/codegen/mips/CodegenCommon.cc
index 3645643..8dbb9a3 100644
--- a/src/compiler/codegen/mips/CodegenCommon.cc
+++ b/src/compiler/codegen/mips/CodegenCommon.cc
@@ -26,9 +26,6 @@ namespace art {
  * applicable directory below this one.
  */
 
-/* Track exercised opcodes */
-static int opcodeCoverage[kNumPackedOpcodes];
-
 static void setMemRefType(MipsLIR *lir, bool isLoad, int memType)
 {
     /* MIPSTODO simplify setMemRefType() */
@@ -230,46 +227,13 @@ STATIC void setupResourceMasks(MipsLIR *lir)
 }
 
 /*
- * Set up the accurate resource mask for branch instructions
- */
-static void relaxBranchMasks(MipsLIR *lir)
-{
-    int flags = EncodingMap[lir->opcode].flags;
-
-    /* Make sure only branch instructions are passed here */
-    DCHECK(flags & IS_BRANCH);
-
-    lir->defMask |= ENCODE_REG_PC;
-    lir->useMask |= ENCODE_REG_PC;
-
-
-    if (flags & REG_DEF_LR) {
-        lir->defMask |= ENCODE_REG_LR;
-    }
-
-    if (flags & (REG_USE0 | REG_USE1 | REG_USE2 | REG_USE3)) {
-        int i;
-
-        for (i = 0; i < 4; i++) {
-            if (flags & (1 << (kRegUse0 + i))) {
-                setupRegMask(&lir->useMask, lir->operands[i]);
-            }
-        }
-    }
-
-    if (flags & USES_CCODES) {
-        lir->useMask |= ENCODE_CCODE;
-    }
-}
-
-/*
  * The following are building blocks to construct low-level IRs with 0 - 4
  * operands.
  */
-static MipsLIR *newLIR0(CompilationUnit *cUnit, MipsOpCode opcode)
+MipsLIR *newLIR0(CompilationUnit *cUnit, MipsOpCode opcode)
 {
     MipsLIR *insn = (MipsLIR *) oatNew(cUnit, sizeof(MipsLIR), true, kAllocLIR);
-    DCHECK(isPseudoOpCode(opcode) || (EncodingMap[opcode].flags & NO_OPERAND));
+    DCHECK(isPseudoOpcode(opcode) || (EncodingMap[opcode].flags & NO_OPERAND));
     insn->opcode = opcode;
     setupResourceMasks(insn);
     insn->generic.dalvikOffset = cUnit->currentDalvikOffset;
@@ -277,11 +241,11 @@ static MipsLIR *newLIR0(CompilationUnit *cUnit, MipsOpCode opcode)
     return insn;
 }
 
-static MipsLIR *newLIR1(CompilationUnit *cUnit, MipsOpCode opcode,
+MipsLIR *newLIR1(CompilationUnit *cUnit, MipsOpCode opcode,
                            int dest)
 {
     MipsLIR *insn = (MipsLIR *) oatNew(cUnit, sizeof(MipsLIR), true, kAllocLIR);
-    DCHECK(isPseudoOpCode(opcode) || (EncodingMap[opcode].flags & IS_UNARY_OP));
+    DCHECK(isPseudoOpcode(opcode) || (EncodingMap[opcode].flags & IS_UNARY_OP));
     insn->opcode = opcode;
     insn->operands[0] = dest;
     setupResourceMasks(insn);
@@ -290,11 +254,11 @@ static MipsLIR *newLIR1(CompilationUnit *cUnit, MipsOpCode opcode,
     return insn;
 }
 
-static MipsLIR *newLIR2(CompilationUnit *cUnit, MipsOpCode opcode,
+MipsLIR *newLIR2(CompilationUnit *cUnit, MipsOpCode opcode,
                            int dest, int src1)
 {
     MipsLIR *insn = (MipsLIR *) oatNew(cUnit, sizeof(MipsLIR), true, kAllocLIR);
-    DCHECK(isPseudoOpCode(opcode) ||
+    DCHECK(isPseudoOpcode(opcode) ||
            (EncodingMap[opcode].flags & IS_BINARY_OP));
     insn->opcode = opcode;
     insn->operands[0] = dest;
@@ -305,14 +269,14 @@ static MipsLIR *newLIR2(CompilationUnit *cUnit, MipsOpCode opcode,
     return insn;
 }
 
-static MipsLIR *newLIR3(CompilationUnit *cUnit, MipsOpCode opcode,
+MipsLIR *newLIR3(CompilationUnit *cUnit, MipsOpCode opcode,
                            int dest, int src1, int src2)
 {
     MipsLIR *insn = (MipsLIR *) oatNew(cUnit, sizeof(MipsLIR), true, kAllocLIR);
     if (!(EncodingMap[opcode].flags & IS_TERTIARY_OP)) {
         LOG(FATAL) << "Bad LIR3: " << EncodingMap[opcode].name;
     }
-    DCHECK(isPseudoOpCode(opcode) ||
+    DCHECK(isPseudoOpcode(opcode) ||
            (EncodingMap[opcode].flags & IS_TERTIARY_OP));
     insn->opcode = opcode;
     insn->operands[0] = dest;
@@ -324,11 +288,11 @@ static MipsLIR *newLIR3(CompilationUnit *cUnit, MipsOpCode opcode,
     return insn;
 }
 
-static MipsLIR *newLIR4(CompilationUnit *cUnit, MipsOpCode opcode,
+MipsLIR *newLIR4(CompilationUnit *cUnit, MipsOpCode opcode,
                            int dest, int src1, int src2, int info)
 {
     MipsLIR *insn = (MipsLIR *) oatNew(cUnit, sizeof(MipsLIR), true, kAllocLIR);
-    DCHECK(isPseudoOpCode(opcode) ||
+    DCHECK(isPseudoOpcode(opcode) ||
            (EncodingMap[opcode].flags & IS_QUAD_OP));
     insn->opcode = opcode;
     insn->operands[0] = dest;
@@ -342,36 +306,12 @@ static MipsLIR *newLIR4(CompilationUnit *cUnit, MipsOpCode opcode,
 }
 
 /*
- * The following are building blocks to insert constants into the pool or
- * instruction streams.
- */
-
-/* Add a 32-bit constant either in the constant pool or mixed with code */
-static MipsLIR *addWordData(CompilationUnit *cUnit, LIR **constantListP,
-                           int value)
-{
-    /* Add the constant to the literal pool */
-    if (constantListP) {
-        MipsLIR *newValue = (MipsLIR *) oatNew(cUnit, sizeof(MipsLIR), true,
-                                               kAllocData);
-        newValue->operands[0] = value;
-        newValue->generic.next = *constantListP;
-        *constantListP = (LIR *) newValue;
-        return newValue;
-    } else {
-        /* Add the constant in the middle of code stream */
-        newLIR1(cUnit, kMips32BitData, value);
-    }
-    return NULL;
-}
-
-/*
- * Generate an kMipsPseudoBarrier marker to indicate the boundary of special
+ * Generate an kPseudoBarrier marker to indicate the boundary of special
  * blocks.
  */
 static void genBarrier(CompilationUnit *cUnit)
 {
-    MipsLIR *barrier = newLIR0(cUnit, kMipsPseudoBarrier);
+    MipsLIR *barrier = newLIR0(cUnit, kPseudoBarrier);
     /* Mark all resources as being clobbered */
     barrier->defMask = -1;
 }
diff --git a/src/compiler/codegen/mips/FP/MipsFP.cc b/src/compiler/codegen/mips/FP/MipsFP.cc
index fd07a34..7eb2a1a 100644
--- a/src/compiler/codegen/mips/FP/MipsFP.cc
+++ b/src/compiler/codegen/mips/FP/MipsFP.cc
@@ -21,7 +21,7 @@ extern void oatFlushRegWideForV5TEVFP(CompilationUnit *cUnit,
 extern void oatFlushRegForV5TEVFP(CompilationUnit *cUnit, int reg);
 
 /* First, flush any registers associated with this value */
-static void loadValueAddress(CompilationUnit *cUnit, RegLocation rlSrc,
+void loadValueAddress(CompilationUnit *cUnit, RegLocation rlSrc,
                              int rDest)
 {
     UNIMPLEMENTED(FATAL) << "Need Mips implementation";
@@ -253,7 +253,6 @@ static bool genConversion(CompilationUnit *cUnit, MIR *mir)
     int op = kMipsNop;
     int srcReg;
     RegLocation rlResult;
-
     switch (opcode) {
         case OP_INT_TO_FLOAT:
             longSrc = false;
diff --git a/src/compiler/codegen/mips/Mips32/Factory.cc b/src/compiler/codegen/mips/Mips32/Factory.cc
index ffbb223..f76adff 100644
--- a/src/compiler/codegen/mips/Mips32/Factory.cc
+++ b/src/compiler/codegen/mips/Mips32/Factory.cc
@@ -38,21 +38,17 @@ static int fpTemps[] = {r_F0, r_F1, r_F2, r_F3, r_F4, r_F5, r_F6, r_F7,
                         r_F8, r_F9, r_F10, r_F11, r_F12, r_F13, r_F14, r_F15};
 #endif
 
-static void storePair(CompilationUnit *cUnit, int base, int lowReg,
-                      int highReg);
-static void loadPair(CompilationUnit *cUnit, int base, int lowReg, int highReg);
-static MipsLIR *loadWordDisp(CompilationUnit *cUnit, int rBase, int displacement,
-                            int rDest);
-static MipsLIR *storeWordDisp(CompilationUnit *cUnit, int rBase,
-                             int displacement, int rSrc);
-static MipsLIR *genRegRegCheck(CompilationUnit *cUnit,
-                              MipsConditionCode cond,
-                              int reg1, int reg2, int dOffset,
-                              MipsLIR *pcrLabel);
-static MipsLIR *loadConstant(CompilationUnit *cUnit, int rDest, int value);
+void storePair(CompilationUnit *cUnit, int base, int lowReg,
+               int highReg);
+void loadPair(CompilationUnit *cUnit, int base, int lowReg, int highReg);
+MipsLIR *loadWordDisp(CompilationUnit *cUnit, int rBase, int displacement,
+                      int rDest);
+MipsLIR *storeWordDisp(CompilationUnit *cUnit, int rBase,
+                       int displacement, int rSrc);
+MipsLIR *loadConstant(CompilationUnit *cUnit, int rDest, int value);
 
 #ifdef __mips_hard_float
-static MipsLIR *fpRegCopy(CompilationUnit *cUnit, int rDest, int rSrc)
+MipsLIR *fpRegCopy(CompilationUnit *cUnit, int rDest, int rSrc)
 {
     MipsLIR* res = (MipsLIR *) oatNew(cUnit, sizeof(MipsLIR), true, kAllocLIR);
     res->operands[0] = rDest;
@@ -94,8 +90,8 @@ static MipsLIR *fpRegCopy(CompilationUnit *cUnit, int rDest, int rSrc)
  * 1) rDest is freshly returned from oatAllocTemp or
  * 2) The codegen is under fixed register usage
  */
-static MipsLIR *loadConstantNoClobber(CompilationUnit *cUnit, int rDest,
-                                     int value)
+MipsLIR *loadConstantNoClobber(CompilationUnit *cUnit, int rDest,
+                               int value)
 {
     MipsLIR *res;
 
@@ -135,7 +131,7 @@ static MipsLIR *loadConstantNoClobber(CompilationUnit *cUnit, int rDest,
  * Load an immediate value into a fixed or temp register.  Target
  * register is clobbered, and marked inUse.
  */
-static MipsLIR *loadConstant(CompilationUnit *cUnit, int rDest, int value)
+MipsLIR *loadConstant(CompilationUnit *cUnit, int rDest, int value)
 {
     if (oatIsTemp(cUnit, rDest)) {
         oatClobber(cUnit, rDest);
@@ -144,24 +140,7 @@ static MipsLIR *loadConstant(CompilationUnit *cUnit, int rDest, int value)
     return loadConstantNoClobber(cUnit, rDest, value);
 }
 
-/*
- * Load a class pointer value into a fixed or temp register.  Target
- * register is clobbered, and marked inUse.
- */
-static MipsLIR *loadClassPointer(CompilationUnit *cUnit, int rDest, int value)
-{
-    MipsLIR *res;
-    if (oatIsTemp(cUnit, rDest)) {
-        oatClobber(cUnit, rDest);
-        oatMarkInUse(cUnit, rDest);
-    }
-    res = newLIR2(cUnit, kMipsLui, rDest, value>>16);
-    if (value & 0xffff)
-        newLIR3(cUnit, kMipsOri, rDest, rDest, value);
-    return res;
-}
-
-static MipsLIR *opNone(CompilationUnit *cUnit, OpKind op)
+MipsLIR *opNone(CompilationUnit *cUnit, OpKind op)
 {
     MipsLIR *res;
     MipsOpCode opcode = kMipsNop;
@@ -176,7 +155,27 @@ static MipsLIR *opNone(CompilationUnit *cUnit, OpKind op)
     return res;
 }
 
-static MipsLIR *opCompareBranch(CompilationUnit *cUnit, MipsOpCode opc, int rs, int rt)
+
+MipsLIR *opCmpBranchCC(CompilationUnit *cUnit, MipsConditionCode cc,
+                           int rs, int rt)
+{
+    UNIMPLEMENTED(FATAL);
+    return 0;
+}
+MipsLIR *opCmpImmBranchCC(CompilationUnit *cUnit, MipsConditionCode cc,
+                           int rs, int immVal)
+{
+    UNIMPLEMENTED(FATAL);
+    return 0;
+}
+MipsLIR *opCmpImmBranch(CompilationUnit *cUnit, MipsOpCode cc,
+                           int rs, int immVal)
+{
+    UNIMPLEMENTED(FATAL);
+    return 0;
+}
+
+MipsLIR *opCmpBranch(CompilationUnit *cUnit, MipsOpCode opc, int rs, int rt)
 {
     MipsLIR *res;
     if (rt < 0) {
@@ -189,9 +188,9 @@ static MipsLIR *opCompareBranch(CompilationUnit *cUnit, MipsOpCode opc, int rs,
     return res;
 }
 
-static MipsLIR *loadMultiple(CompilationUnit *cUnit, int rBase, int rMask);
+MipsLIR *loadMultiple(CompilationUnit *cUnit, int rBase, int rMask);
 
-static MipsLIR *opReg(CompilationUnit *cUnit, OpKind op, int rDestSrc)
+MipsLIR *opReg(CompilationUnit *cUnit, OpKind op, int rDestSrc)
 {
     MipsOpCode opcode = kMipsNop;
     switch (op) {
@@ -204,8 +203,8 @@ static MipsLIR *opReg(CompilationUnit *cUnit, OpKind op, int rDestSrc)
     return newLIR2(cUnit, opcode, r_RA, rDestSrc);
 }
 
-static MipsLIR *opRegRegImm(CompilationUnit *cUnit, OpKind op, int rDest,
-                           int rSrc1, int value);
+MipsLIR *opRegRegImm(CompilationUnit *cUnit, OpKind op, int rDest,
+                     int rSrc1, int value);
 MipsLIR *opRegImm(CompilationUnit *cUnit, OpKind op, int rDestSrc1,
                   int value)
 {
@@ -238,7 +237,7 @@ MipsLIR *opRegImm(CompilationUnit *cUnit, OpKind op, int rDestSrc1,
     return res;
 }
 
-static MipsLIR *opRegRegReg(CompilationUnit *cUnit, OpKind op, int rDest,
+MipsLIR *opRegRegReg(CompilationUnit *cUnit, OpKind op, int rDest,
                            int rSrc1, int rSrc2)
 {
     MipsOpCode opcode = kMipsNop;
@@ -277,7 +276,7 @@ static MipsLIR *opRegRegReg(CompilationUnit *cUnit, OpKind op, int rDest,
     return newLIR3(cUnit, opcode, rDest, rSrc1, rSrc2);
 }
 
-static MipsLIR *opRegRegImm(CompilationUnit *cUnit, OpKind op, int rDest,
+MipsLIR *opRegRegImm(CompilationUnit *cUnit, OpKind op, int rDest,
                            int rSrc1, int value)
 {
     MipsLIR *res;
@@ -412,7 +411,7 @@ MipsLIR *opRegReg(CompilationUnit *cUnit, OpKind op, int rDestSrc1,
     return newLIR2(cUnit, opcode, rDestSrc1, rSrc2);
 }
 
-static MipsLIR *loadConstantValueWide(CompilationUnit *cUnit, int rDestLo,
+MipsLIR *loadConstantValueWide(CompilationUnit *cUnit, int rDestLo,
                                      int rDestHi, int valLo, int valHi)
 {
     MipsLIR *res;
@@ -422,7 +421,7 @@ static MipsLIR *loadConstantValueWide(CompilationUnit *cUnit, int rDestLo,
 }
 
 /* Load value from base + scaled index. */
-static MipsLIR *loadBaseIndexed(CompilationUnit *cUnit, int rBase,
+MipsLIR *loadBaseIndexed(CompilationUnit *cUnit, int rBase,
                                int rIndex, int rDest, int scale, OpSize size)
 {
     MipsLIR *first = NULL;
@@ -479,7 +478,7 @@ static MipsLIR *loadBaseIndexed(CompilationUnit *cUnit, int rBase,
 }
 
 /* store value base base + scaled index. */
-static MipsLIR *storeBaseIndexed(CompilationUnit *cUnit, int rBase,
+MipsLIR *storeBaseIndexed(CompilationUnit *cUnit, int rBase,
                                 int rIndex, int rSrc, int scale, OpSize size)
 {
     MipsLIR *first = NULL;
@@ -531,7 +530,7 @@ static MipsLIR *storeBaseIndexed(CompilationUnit *cUnit, int rBase,
     return first;
 }
 
-static MipsLIR *loadMultiple(CompilationUnit *cUnit, int rBase, int rMask)
+MipsLIR *loadMultiple(CompilationUnit *cUnit, int rBase, int rMask)
 {
     int i;
     int loadCnt = 0;
@@ -553,7 +552,7 @@ static MipsLIR *loadMultiple(CompilationUnit *cUnit, int rBase, int rMask)
     return res; /* NULL always returned which should be ok since no callers use it */
 }
 
-static MipsLIR *storeMultiple(CompilationUnit *cUnit, int rBase, int rMask)
+MipsLIR *storeMultiple(CompilationUnit *cUnit, int rBase, int rMask)
 {
     int i;
     int storeCnt = 0;
@@ -575,7 +574,7 @@ static MipsLIR *storeMultiple(CompilationUnit *cUnit, int rBase, int rMask)
     return res; /* NULL always returned which should be ok since no callers use it */
 }
 
-static MipsLIR *loadBaseDispBody(CompilationUnit *cUnit, MIR *mir, int rBase,
+MipsLIR *loadBaseDispBody(CompilationUnit *cUnit, MIR *mir, int rBase,
                                 int displacement, int rDest, int rDestHi,
                                 OpSize size, int sReg)
 /*
@@ -681,7 +680,7 @@ static MipsLIR *loadBaseDispBody(CompilationUnit *cUnit, MIR *mir, int rBase,
     return load;
 }
 
-static MipsLIR *loadBaseDisp(CompilationUnit *cUnit, MIR *mir, int rBase,
+MipsLIR *loadBaseDisp(CompilationUnit *cUnit, MIR *mir, int rBase,
                             int displacement, int rDest, OpSize size,
                             int sReg)
 {
@@ -689,15 +688,15 @@ static MipsLIR *loadBaseDisp(CompilationUnit *cUnit, MIR *mir, int rBase,
                             size, sReg);
 }
 
-static MipsLIR *loadBaseDispWide(CompilationUnit *cUnit, MIR *mir, int rBase,
-                                int displacement, int rDestLo, int rDestHi,
+MipsLIR *loadBaseDispWide(CompilationUnit *cUnit, MIR *mir, int rBase,
+                          int displacement, int rDestLo, int rDestHi,
                                 int sReg)
 {
     return loadBaseDispBody(cUnit, mir, rBase, displacement, rDestLo, rDestHi,
                             kLong, sReg);
 }
 
-static MipsLIR *storeBaseDispBody(CompilationUnit *cUnit, int rBase,
+MipsLIR *storeBaseDispBody(CompilationUnit *cUnit, int rBase,
                                  int displacement, int rSrc, int rSrcHi,
                                  OpSize size)
 {
@@ -786,31 +785,25 @@ static MipsLIR *storeBaseDispBody(CompilationUnit *cUnit, int rBase,
     return res;
 }
 
-static MipsLIR *storeBaseDisp(CompilationUnit *cUnit, int rBase,
-                             int displacement, int rSrc, OpSize size)
+MipsLIR *storeBaseDisp(CompilationUnit *cUnit, int rBase,
+                       int displacement, int rSrc, OpSize size)
 {
     return storeBaseDispBody(cUnit, rBase, displacement, rSrc, -1, size);
 }
 
-static MipsLIR *storeBaseDispWide(CompilationUnit *cUnit, int rBase,
-                                 int displacement, int rSrcLo, int rSrcHi)
+MipsLIR *storeBaseDispWide(CompilationUnit *cUnit, int rBase,
+                           int displacement, int rSrcLo, int rSrcHi)
 {
     return storeBaseDispBody(cUnit, rBase, displacement, rSrcLo, rSrcHi, kLong);
 }
 
-static void storePair(CompilationUnit *cUnit, int base, int lowReg, int highReg)
-{
-    storeWordDisp(cUnit, base, LOWORD_OFFSET, lowReg);
-    storeWordDisp(cUnit, base, HIWORD_OFFSET, highReg);
-}
-
-static void loadPair(CompilationUnit *cUnit, int base, int lowReg, int highReg)
+void loadPair(CompilationUnit *cUnit, int base, int lowReg, int highReg)
 {
     loadWordDisp(cUnit, base, LOWORD_OFFSET , lowReg);
     loadWordDisp(cUnit, base, HIWORD_OFFSET , highReg);
 }
 
-static MipsLIR* genRegCopyNoInsert(CompilationUnit *cUnit, int rDest, int rSrc)
+MipsLIR* genRegCopyNoInsert(CompilationUnit *cUnit, int rDest, int rSrc)
 {
     MipsLIR* res;
     MipsOpCode opcode;
@@ -831,14 +824,14 @@ static MipsLIR* genRegCopyNoInsert(CompilationUnit *cUnit, int rDest, int rSrc)
     return res;
 }
 
-static MipsLIR* genRegCopy(CompilationUnit *cUnit, int rDest, int rSrc)
+MipsLIR* genRegCopy(CompilationUnit *cUnit, int rDest, int rSrc)
 {
     MipsLIR *res = genRegCopyNoInsert(cUnit, rDest, rSrc);
     oatAppendLIR(cUnit, (LIR*)res);
     return res;
 }
 
-static void genRegCopyWide(CompilationUnit *cUnit, int destLo, int destHi,
+void genRegCopyWide(CompilationUnit *cUnit, int destLo, int destHi,
                            int srcLo, int srcHi)
 {
 #ifdef __mips_hard_float
@@ -881,10 +874,10 @@ static void genRegCopyWide(CompilationUnit *cUnit, int destLo, int destHi,
 #endif
 }
 
-static inline MipsLIR *genRegImmCheck(CompilationUnit *cUnit,
-                                     MipsConditionCode cond, int reg,
-                                     int checkValue, int dOffset,
-                                     MipsLIR *pcrLabel)
+inline MipsLIR *genRegImmCheck(CompilationUnit *cUnit,
+                               MipsConditionCode cond, int reg,
+                               int checkValue, int dOffset,
+                               MipsLIR *pcrLabel)
 {
     MipsLIR *branch = NULL;
 
diff --git a/src/compiler/codegen/mips/Mips32/Gen.cc b/src/compiler/codegen/mips/Mips32/Gen.cc
index f49cdab..8801692 100644
--- a/src/compiler/codegen/mips/Mips32/Gen.cc
+++ b/src/compiler/codegen/mips/Mips32/Gen.cc
@@ -62,10 +62,192 @@ bool genShiftOpLong(CompilationUnit* cUnit, MIR* mir,
 bool genArithOpIntLit(CompilationUnit* cUnit, MIR* mir,
                              RegLocation rlDest, RegLocation rlSrc,
                              int lit) { return 0; }
+void oatArchDump(void) {};
+void genDebuggerUpdate(CompilationUnit* cUnit, int32_t offset) {};
 
 
 
 
+STATIC bool genConversionCall(CompilationUnit* cUnit, MIR* mir, int funcOffset,
+                                     int srcSize, int tgtSize)
+{
+    UNIMPLEMENTED(FATAL) << "Need Mips implementation";
+    return 0;
+#if 0
+    /*
+     * Don't optimize the register usage since it calls out to support
+     * functions
+     */
+    RegLocation rlSrc;
+    RegLocation rlDest;
+    oatFlushAllRegs(cUnit);   /* Send everything to home location */
+    loadWordDisp(cUnit, rSELF, funcOffset, rLR);
+    if (srcSize == 1) {
+        rlSrc = oatGetSrc(cUnit, mir, 0);
+        loadValueDirectFixed(cUnit, rlSrc, r0);
+    } else {
+        rlSrc = oatGetSrcWide(cUnit, mir, 0, 1);
+        loadValueDirectWideFixed(cUnit, rlSrc, r0, r1);
+    }
+    callRuntimeHelper(cUnit, rLR);
+    if (tgtSize == 1) {
+        RegLocation rlResult;
+        rlDest = oatGetDest(cUnit, mir, 0);
+        rlResult = oatGetReturn(cUnit);
+        storeValue(cUnit, rlDest, rlResult);
+    } else {
+        RegLocation rlResult;
+        rlDest = oatGetDestWide(cUnit, mir, 0, 1);
+        rlResult = oatGetReturnWide(cUnit);
+        storeValueWide(cUnit, rlDest, rlResult);
+    }
+    return false;
+#endif
+}
+
+bool genArithOpFloatPortable(CompilationUnit* cUnit, MIR* mir,
+                                    RegLocation rlDest, RegLocation rlSrc1,
+                                    RegLocation rlSrc2)
+{
+    UNIMPLEMENTED(FATAL) << "Need Mips implementation";
+    return 0;
+#if 0
+    RegLocation rlResult;
+    int funcOffset;
+
+    switch (mir->dalvikInsn.opcode) {
+        case OP_ADD_FLOAT_2ADDR:
+        case OP_ADD_FLOAT:
+            funcOffset = OFFSETOF_MEMBER(Thread, pFadd);
+            break;
+        case OP_SUB_FLOAT_2ADDR:
+        case OP_SUB_FLOAT:
+            funcOffset = OFFSETOF_MEMBER(Thread, pFsub);
+            break;
+        case OP_DIV_FLOAT_2ADDR:
+        case OP_DIV_FLOAT:
+            funcOffset = OFFSETOF_MEMBER(Thread, pFdiv);
+            break;
+        case OP_MUL_FLOAT_2ADDR:
+        case OP_MUL_FLOAT:
+            funcOffset = OFFSETOF_MEMBER(Thread, pFmul);
+            break;
+        case OP_REM_FLOAT_2ADDR:
+        case OP_REM_FLOAT:
+            funcOffset = OFFSETOF_MEMBER(Thread, pFmodf);
+            break;
+        case OP_NEG_FLOAT: {
+            genNegFloat(cUnit, rlDest, rlSrc1);
+            return false;
+        }
+        default:
+            return true;
+    }
+    oatFlushAllRegs(cUnit);   /* Send everything to home location */
+    loadWordDisp(cUnit, rSELF, funcOffset, rLR);
+    loadValueDirectFixed(cUnit, rlSrc1, r0);
+    loadValueDirectFixed(cUnit, rlSrc2, r1);
+    callRuntimeHelper(cUnit, rLR);
+    rlResult = oatGetReturn(cUnit);
+    storeValue(cUnit, rlDest, rlResult);
+    return false;
+#endif
+}
+
+bool genArithOpDoublePortable(CompilationUnit* cUnit, MIR* mir,
+                                     RegLocation rlDest, RegLocation rlSrc1,
+                                     RegLocation rlSrc2)
+{
+    UNIMPLEMENTED(FATAL) << "Need Mips implementation";
+    return 0;
+#if 0
+    RegLocation rlResult;
+    int funcOffset;
+
+    switch (mir->dalvikInsn.opcode) {
+        case OP_ADD_DOUBLE_2ADDR:
+        case OP_ADD_DOUBLE:
+            funcOffset = OFFSETOF_MEMBER(Thread, pDadd);
+            break;
+        case OP_SUB_DOUBLE_2ADDR:
+        case OP_SUB_DOUBLE:
+            funcOffset = OFFSETOF_MEMBER(Thread, pDsub);
+            break;
+        case OP_DIV_DOUBLE_2ADDR:
+        case OP_DIV_DOUBLE:
+            funcOffset = OFFSETOF_MEMBER(Thread, pDdiv);
+            break;
+        case OP_MUL_DOUBLE_2ADDR:
+        case OP_MUL_DOUBLE:
+            funcOffset = OFFSETOF_MEMBER(Thread, pDmul);
+            break;
+        case OP_REM_DOUBLE_2ADDR:
+        case OP_REM_DOUBLE:
+            funcOffset = OFFSETOF_MEMBER(Thread, pFmod);
+            break;
+        case OP_NEG_DOUBLE: {
+            genNegDouble(cUnit, rlDest, rlSrc1);
+            return false;
+        }
+        default:
+            return true;
+    }
+    oatFlushAllRegs(cUnit);   /* Send everything to home location */
+    loadWordDisp(cUnit, rSELF, funcOffset, rLR);
+    loadValueDirectWideFixed(cUnit, rlSrc1, r0, r1);
+    loadValueDirectWideFixed(cUnit, rlSrc2, r2, r3);
+    callRuntimeHelper(cUnit, rLR);
+    rlResult = oatGetReturnWide(cUnit);
+    storeValueWide(cUnit, rlDest, rlResult);
+    return false;
+#endif
+}
+
+bool genConversionPortable(CompilationUnit* cUnit, MIR* mir)
+{
+    UNIMPLEMENTED(FATAL) << "Need Mips implementation";
+    return 0;
+#if 0
+    Opcode opcode = mir->dalvikInsn.opcode;
+
+    switch (opcode) {
+        case OP_INT_TO_FLOAT:
+            return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread, pI2f),
+                                     1, 1);
+        case OP_FLOAT_TO_INT:
+            return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread, pF2iz),
+                                     1, 1);
+        case OP_DOUBLE_TO_FLOAT:
+            return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread, pD2f),
+                                     2, 1);
+        case OP_FLOAT_TO_DOUBLE:
+            return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread, pF2d),
+                                     1, 2);
+        case OP_INT_TO_DOUBLE:
+            return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread, pI2d),
+                                     1, 2);
+        case OP_DOUBLE_TO_INT:
+            return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread, pD2iz),
+                                     2, 1);
+        case OP_FLOAT_TO_LONG:
+            return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread,
+                                     pF2l), 1, 2);
+        case OP_LONG_TO_FLOAT:
+            return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread, pL2f),
+                                     2, 1);
+        case OP_DOUBLE_TO_LONG:
+            return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread,
+                                     pD2l), 2, 2);
+        case OP_LONG_TO_DOUBLE:
+            return genConversionCall(cUnit, mir, OFFSETOF_MEMBER(Thread, pL2d),
+                                     2, 2);
+        default:
+            return true;
+    }
+    return false;
+#endif
+}
+
 
 
 
@@ -102,7 +284,7 @@ STATIC inline s4 s4FromSwitchData(const void* switchData) {
 }
 #endif
 /*
- * Insert a kMipsPseudoCaseLabel at the beginning of the Dalvik
+ * Insert a kPseudoCaseLabel at the beginning of the Dalvik
  * offset vaddr.  This label will be used to fix up the case
  * branch table during the assembly phase.  Be sure to set
  * all resource flags on this to prevent code motion across
@@ -117,7 +299,7 @@ STATIC MipsLIR* insertCaseLabel(CompilationUnit* cUnit, int vaddr, int keyVal)
     }
     MipsLIR* newLabel = (MipsLIR*)oatNew(cUnit, sizeof(MipsLIR), true, kAllocLIR);
     newLabel->generic.dalvikOffset = vaddr;
-    newLabel->opcode = kMipsPseudoCaseLabel;
+    newLabel->opcode = kPseudoCaseLabel;
     newLabel->operands[0] = keyVal;
     oatInsertLIRAfter(it->second, (LIR*)newLabel);
     return newLabel;
@@ -269,7 +451,7 @@ STATIC void genSparseSwitch(CompilationUnit* cUnit, MIR* mir,
     int rIdx = oatAllocTemp(cUnit);
     loadConstant(cUnit, rIdx, size);
     // Establish loop branch target
-    MipsLIR* target = newLIR0(cUnit, kMipsPseudoTargetLabel);
+    MipsLIR* target = newLIR0(cUnit, kPseudoTargetLabel);
     target->defMask = ENCODE_ALL;
     // Load next key/disp
     newLIR2(cUnit, kThumb2LdmiaWB, rBase, (1 << rKey) | (1 << rDisp));
@@ -331,7 +513,7 @@ STATIC void genPackedSwitch(CompilationUnit* cUnit, MIR* mir,
     tabRec->bxInst = switchBranch;
 
     /* branchOver target here */
-    MipsLIR* target = newLIR0(cUnit, kMipsPseudoTargetLabel);
+    MipsLIR* target = newLIR0(cUnit, kPseudoTargetLabel);
     target->defMask = ENCODE_ALL;
     branchOver->generic.target = (LIR*)target;
 #endif
diff --git a/src/compiler/codegen/mips/MipsLIR.h b/src/compiler/codegen/mips/MipsLIR.h
index a6f426e..44f0c5a 100644
--- a/src/compiler/codegen/mips/MipsLIR.h
+++ b/src/compiler/codegen/mips/MipsLIR.h
@@ -193,42 +193,6 @@ typedef enum ResourceEncodingPos {
 #define DECODE_ALIAS_INFO_REG(X)        (X & 0xffff)
 #define DECODE_ALIAS_INFO_WIDE(X)       ((X & 0x80000000) ? 1 : 0)
 
-typedef enum OpKind {
-    kOpMov,
-    kOpMvn,
-    kOpCmp,
-    kOpLsl,
-    kOpLsr,
-    kOpAsr,
-    kOpRor,
-    kOpNot,
-    kOpAnd,
-    kOpOr,
-    kOpXor,
-    kOpNeg,
-    kOpAdd,
-    kOpAdc,
-    kOpSub,
-    kOpSbc,
-    kOpRsub,
-    kOpMul,
-    kOpDiv,
-    kOpRem,
-    kOpBic,
-    kOpCmn,
-    kOpTst,
-    kOpBkpt,
-    kOpBlx,
-    kOpPush,
-    kOpPop,
-    kOp2Char,
-    kOp2Short,
-    kOp2Byte,
-    kOpCondBr,
-    kOpUncondBr,
-    kOpInvalid,
-} OpKind;
-
 /*
  * FIXME:
  * Originally had r4PC as r_S0, rFP as r_S1, rSELF as r_S2, rINST as r_S4
@@ -240,8 +204,13 @@ typedef enum OpKind {
 #define rSELF r_S1
 #define rSP r_SP
 
-/* FIXME: don't do this - find and fix all rLR's */
-#define rLR r_RA
+#define rARG0 r_ARG0
+#define rARG1 r_ARG1
+#define rARG2 r_ARG2
+#define rARG3 r_ARG3
+
+#define rRET0 r_V0
+#define rRET1 r_V1
 
 /*
  * Annotate special-purpose core registers:
@@ -376,7 +345,7 @@ typedef enum MipsThrowKind {
     kMipsThrowStackOverflow,
 } MipsThrowKind;
 
-#define isPseudoOpCode(opCode) ((int)(opCode) < 0)
+#define isPseudoOpcode(opCode) ((int)(opCode) < 0)
 
 /*
  * The following enum defines the list of supported Thumb instructions by the
@@ -384,21 +353,21 @@ typedef enum MipsThrowKind {
  * Assemble.c.
  */
 typedef enum MipsOpCode {
-    kMipsPseudoSuspendTarget = -15,
-    kMipsPseudoThrowTarget = -14,
-    kMipsPseudoCaseLabel = -13,
-    kMipsPseudoMethodEntry = -12,
-    kMipsPseudoMethodExit = -11,
-    kMipsPseudoBarrier = -10,
-    kMipsPseudoExtended = -9,
-    kMipsPseudoSSARep = -8,
-    kMipsPseudoEntryBlock = -7,
-    kMipsPseudoExitBlock = -6,
-    kMipsPseudoTargetLabel = -5,
-    kMipsPseudoDalvikByteCodeBoundary = -4,
-    kMipsPseudoPseudoAlign4 = -3,
-    kMipsPseudoEHBlockLabel = -2,
-    kMipsPseudoNormalBlockLabel = -1,
+    kPseudoSuspendTarget = -15,
+    kPseudoThrowTarget = -14,
+    kPseudoCaseLabel = -13,
+    kPseudoMethodEntry = -12,
+    kPseudoMethodExit = -11,
+    kPseudoBarrier = -10,
+    kPseudoExtended = -9,
+    kPseudoSSARep = -8,
+    kPseudoEntryBlock = -7,
+    kPseudoExitBlock = -6,
+    kPseudoTargetLabel = -5,
+    kPseudoDalvikByteCodeBoundary = -4,
+    kPseudoPseudoAlign4 = -3,
+    kPseudoEHBlockLabel = -2,
+    kPseudoNormalBlockLabel = -1,
 
     kMipsFirst,
     kMips32BitData = kMipsFirst, /* data [31..0] */
diff --git a/src/compiler/codegen/mips/MipsRallocUtil.cc b/src/compiler/codegen/mips/MipsRallocUtil.cc
index a243415..0dfbfa5 100644
--- a/src/compiler/codegen/mips/MipsRallocUtil.cc
+++ b/src/compiler/codegen/mips/MipsRallocUtil.cc
@@ -28,12 +28,24 @@
 namespace art {
 
 /*
+ * TUNING: is leaf?  Can't just use "hasInvoke" to determine as some
+ * instructions might call out to C/assembly helper functions.  Until
+ * machinery is in place, always spill lr.
+ */
+
+void oatAdjustSpillMask(CompilationUnit* cUnit)
+{
+    cUnit->coreSpillMask |= (1 << r_RA);
+    cUnit->numCoreSpills++;
+}
+
+/*
  * Mark a callee-save fp register as promoted.  Note that
  * vpush/vpop uses contiguous register lists so we must
  * include any holes in the mask.  Associate holes with
  * Dalvik register INVALID_VREG (0xFFFFU).
  */
-STATIC void markPreservedSingle(CompilationUnit* cUnit, int sReg, int reg)
+void oatMarkPreservedSingle(CompilationUnit* cUnit, int sReg, int reg)
 {
     UNIMPLEMENTED(FATAL) << "No support yet for promoted FP regs";
 #if 0
@@ -206,4 +218,10 @@ extern void oatFreeCallTemps(CompilationUnit* cUnit)
     oatFreeTemp(cUnit, r_A3);
 }
 
+/* Convert an instruction to a NOP */
+STATIC void oatNopLIR( LIR* lir)
+{
+    ((MipsLIR*)lir)->flags.isNop = true;
+}
+
 }  // namespace art
diff --git a/src/compiler/codegen/mips/mips/ArchVariant.cc b/src/compiler/codegen/mips/mips/ArchVariant.cc
index 5eca74b..dd46f24 100644
--- a/src/compiler/codegen/mips/mips/ArchVariant.cc
+++ b/src/compiler/codegen/mips/mips/ArchVariant.cc
@@ -25,9 +25,9 @@ namespace art {
  * Determine the initial instruction set to be used for this trace.
  * Later components may decide to change this.
  */
-JitInstructionSetType oatInstructionSet(void)
+OatInstructionSetType oatInstructionSet(void)
 {
-    return DALVIK_OAT_MIPS;
+    return DALVIK_OAT_MIPS32;
 }
 
 /* Architecture-specific initializations and checks go here */
diff --git a/src/compiler/codegen/mips/mips/Codegen.cc b/src/compiler/codegen/mips/mips/Codegen.cc
index 2b71b04..22a7c94 100644
--- a/src/compiler/codegen/mips/mips/Codegen.cc
+++ b/src/compiler/codegen/mips/mips/Codegen.cc
@@ -17,9 +17,6 @@
 #define _CODEGEN_C
 #define TGT_LIR MipsLIR
 
-/* For testing */
-#define __mips_hard_float
-
 #include "../../../Dalvik.h"
 #include "../../../CompilerInternals.h"
 #include "../MipsLIR.h"