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path: root/compiler/dex/quick/arm64/utility_arm64.cc
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* AArch64: Implement InexpensiveConstant methods.Matteo Franchin2014-08-041-48/+158
* AArch64: Add inlining support for ceil(), floor(), rint(), round()Serban Constantinescu2014-08-041-2/+2
* Merge "AArch64: Remove unnecessary work around for sp."Andreas Gampe2014-08-011-13/+15
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| * AArch64: Remove unnecessary work around for sp.Zheng Xu2014-08-041-13/+15
* | Revert "Revert "Enable Load Store Elimination for ARM and ARM64""Serban Constantinescu2014-07-281-0/+20
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* ART: Rework quick entrypoint code in Mir2Lir, cleanupAndreas Gampe2014-07-281-25/+2
* Revert "Enable Load Store Elimination for ARM and ARM64"Bill Buzbee2014-07-271-20/+0
* Enable Load Store Elimination for ARM and ARM64Serban Constantinescu2014-07-271-0/+20
* Merge "AArch64: Fix and enable reverseBytes intrinsic."Andreas Gampe2014-07-111-1/+3
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| * AArch64: Fix and enable reverseBytes intrinsic.Zheng Xu2014-07-101-1/+3
* | Replace memory barriers to better reflect Java needs.Hans Boehm2014-07-111-8/+8
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* Aarch64: fix references handling in Load*Indexed.Matteo Franchin2014-07-061-17/+11
* AArch64: Enable Inlining.Serban Constantinescu2014-07-041-6/+28
* Register promotion support for 64-bit targetsbuzbee2014-07-031-0/+1
* Merge "ART: Quick compiler: More size checks, add TargetReg variants"Andreas Gampe2014-07-011-6/+10
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| * ART: Quick compiler: More size checks, add TargetReg variantsAndreas Gampe2014-07-011-6/+10
* | AArch64: Fix OpRegRegImm64 add/sub for large negative imm.Vladimir Marko2014-07-011-1/+1
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* AArch64: Rename A64_/A32_ register prefix to x/w.Zheng Xu2014-06-301-3/+3
* Merge "AArch64: implement easy division and reminder."Bill Buzbee2014-06-261-1/+1
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| * AArch64: implement easy division and reminder.Matteo Franchin2014-06-191-1/+1
* | Revert "Revert "ART: Split out more cases of Load/StoreRef, volatile as param...Andreas Gampe2014-06-241-19/+53
* | Revert "ART: Split out more cases of Load/StoreRef, volatile as parameter"Andreas Gampe2014-06-241-53/+19
* | ART: Split out more cases of Load/StoreRef, volatile as parameterAndreas Gampe2014-06-231-19/+53
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* ART: Start implementation of OpRegRegRegExtend for ARM64Andreas Gampe2014-06-191-9/+41
* ART: Reserve 8B for float literals on ARM64Andreas Gampe2014-06-181-1/+2
* ART: Change rrr add and sub for ARM64Andreas Gampe2014-06-181-3/+11
* AArch64: improve 64-bit immediates loads.Matteo Franchin2014-06-161-39/+111
* Arm64 hard-floatbuzbee2014-06-161-5/+16
* AArch64: Add support for inlined methodsSerban Constantinescu2014-06-121-2/+2
* AArch64: Enable MOVE_*, some CONST_*, CMP_*.Zheng Xu2014-06-121-7/+43
* Merge "Rewrite use/def masks to support 128 bits."Vladimir Marko2014-06-101-5/+7
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| * Rewrite use/def masks to support 128 bits.Vladimir Marko2014-06-121-5/+7
* | Merge "ART: arm64 explicit stack overflow checks"Bill Buzbee2014-06-111-1/+36
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| * | ART: arm64 explicit stack overflow checksStuart Monteith2014-06-121-1/+36
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* | AArch64: fix MarkGCCard, enabling more MIR opcodes.Matteo Franchin2014-06-101-1/+0
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* AArch64: Fix kOpLsl, rem-float/double.Zheng Xu2014-06-091-3/+3
* AArch64: fixing some assertions.Matteo Franchin2014-05-291-42/+55
* AArch64: Enable LONG_* and INT_* opcodes.Serban Constantinescu2014-05-221-10/+14
* AArch64: fixes in A64 code generation.Matteo Franchin2014-05-191-136/+72
* ART: Add more ThreadOffset in Mir2Lir and backendsAndreas Gampe2014-05-121-1/+6
* Use atomic load/store for volatile IGET/IPUT/SGET/SPUT.Vladimir Marko2014-05-081-1/+15
* AArch64: Change arm64 backend to produce A64 code.Matteo Franchin2014-05-071-697/+631
* Cleanup ARM load/store wide and remove unused param s_reg.Vladimir Marko2014-05-071-9/+9
* Remove LoadBaseDispWide and StoreBaseDispWide.Vladimir Marko2014-05-071-11/+0
* AArch64: Added arm64 quick backend as an arm clone.Matteo Franchin2014-05-061-0/+1149