| Commit message (Collapse) | Author | Age | Files | Lines |
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Also implement spill slot support.
Change-Id: If5e28811e9fbbf3842a258772c633318a2f4fafc
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Change-Id: Ib33e975cee838da97a3bebe04176b5ae8b62f9d5
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The number_of_bits_ field has an unclear intent. Instead, using
storage_size_ * kWordBits when relevant.
Change-Id: I8c13be0d6643de37813fb154296d451f22c298c8
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
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Change-Id: I02eb5671e3304ab062286131745c1366448aff58
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We do three simplifications:
- Split critical edges, for code generation from SSA (new).
- Ensure one back edge per loop, to simplify loop recognition (new).
- Ensure only one pre header for a loop, to simplify SSA creation (existing).
Change-Id: I9bfccd4b236a00486a261078627b091c8a68be33
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This information will be used when computing live ranges of
instructions.
Change-Id: I345ee833c1ccb4a8e725c7976453f6d58d350d74
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