| Commit message (Collapse) | Author | Age | Files | Lines |
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Also implement spill slot support.
Change-Id: If5e28811e9fbbf3842a258772c633318a2f4fafc
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Also fix a brano during SSA construction. The code should
not have been commented out. Added a test to cover what the code
intends.
Change-Id: Ia00ae79dcf75eb0d412f07649d73e7f94dbfb6f0
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This is a "by-the-book" implementation. It currently only deals
with allocating registers, with no hint optimizations.
The changes remaining to make it functional are:
- Allocate spill slots.
- Resolution and placements of Move instructions.
- Connect it to the code generator.
Change-Id: Ie0b2f6ba1b98da85425be721ce4afecd6b4012a4
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The BitVector::Iterator was not iterating over the bits but
rather over indexes of the set bits. Therefore, we rename it
to IndexIterator and provide a BitVector::Indexes() to get
a container-style interface with begin() and end() for range
based for loops.
Also, simplify InsertPhiNodes where the tmp_blocks isn't
needed since the phi_nodes and input_blocks cannot lose any
blocks in subsequent iterations, so we can do the Union()
directly in those bit vectors and we need to repeat the loop
only if we have new input_blocks, rather than on phi_nodes
change. And move the temporary bit vectors to scoped arena.
Change-Id: I6cb87a2f60724eeef67c6aaa34b36ed5acde6d43
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Change-Id: I7ae24afaa4e49276136bf34f4ba7d62db7f28c01
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Change-Id: I02eb5671e3304ab062286131745c1366448aff58
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Code mostly imported from: https://android-review.googlesource.com/#/c/81653/.
Change-Id: I150fe942be0fb270e03fabb19032180f7a065d13
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We do three simplifications:
- Split critical edges, for code generation from SSA (new).
- Ensure one back edge per loop, to simplify loop recognition (new).
- Ensure only one pre header for a loop, to simplify SSA creation (existing).
Change-Id: I9bfccd4b236a00486a261078627b091c8a68be33
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This information will be used when computing live ranges of
instructions.
Change-Id: I345ee833c1ccb4a8e725c7976453f6d58d350d74
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