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* ART: Use StackReference in Quick Stack FrameAndreas Gampe2014-05-291-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | The method reference at the bottom of a quick frame is a stack reference and not a native pointer. This is important for 64b architectures, where the notions do not coincide. Change key methods to have StackReference<mirror::ArtMethod>* parameter instead of mirror::ArtMethod**. Make changes to invoke stubs for 64b archs, change the frame setup for JNI code (both generic JNI and compilers), tie up loose ends. Tested on x86 and x86-64 with host tests. On x86-64, tests succeed with jni compiler activated. x86-64 QCG was not tested. Tested on ARM32 with device tests. Fix ARM64 not saving x19 (used for wSUSPEND) on upcalls. Tested on ARM64 in interpreter-only + generic-jni mode. Fix ARM64 JNI Compiler to work with the CL. Tested on ARM64 in interpreter-only + jni compiler. Change-Id: I77931a0cbadd04d163b3eb8d6f6a6f8740578f13
* Now we have a proper C++ library, use std::unique_ptr.Ian Rogers2014-05-191-2/+2
| | | | | | | Also remove the Android.libcxx.mk and other bits of stlport compatibility mechanics. Change-Id: Icdf7188ba3c79cdf5617672c1cfd0a68ae596a61
* Compatibility layer to transition from UniquePtr to std::unique_ptr.Ian Rogers2014-05-151-1/+1
| | | | | | | | | Use ART_WITH_STLPORT (enabled for the target) to cause the use of UniquePtr, for the host switch to std::unique_ptr. For now the type remains called UniquePtr. Make dalvik compile with clang on the host, move its build to C++11. Change-Id: I5ba8d2757904bc089ed62047ea03de3c0853fb12
* Add Handle/HandleScope and delete SirtRef.Mathieu Chartier2014-05-132-22/+22
| | | | | | | | | | | | | | | | Delete SirtRef and replaced it with Handle. Handles are value types which wrap around StackReference*. Renamed StackIndirectReferenceTable to HandleScope. Added a scoped handle wrapper which wraps around an Object** and restores it in its destructor. Renamed Handle::get -> Get. Bug: 8473721 Change-Id: Idbfebd4f35af629f0f43931b7c5184b334822c7a
* AArch64: Fix the usage of IP0, IP1 as temporary registersSerban Constantinescu2014-05-092-20/+36
| | | | | | | | | This patch fixes the usage of temporary registers by using VIXL's UseScratchRegisterScope. For the primitives used by the trampoline compiler we explicitly exclude IP0, IP1 from the temporary list. Change-Id: Icf9afbabd93214302891ddd536ce03a9c181463b Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
* AArch64: Fix the usage of Thread Register for arm64Serban Constantinescu2014-05-091-17/+23
| | | | | | | | | | | | | | | | This patch cleans-up the usage of x18 as TR for Arm64. As described in the Arm64 Procedure Call Standard, the recommended usage for x18 is to carry inter-procedural state (i.e. ART thread information). However, since x18 is a temporary register there is no guarantee that on calls to external functions x18 is preserved. Thus on JNI calls we need to save and restore x18 before coming back to managed runtime. For the JNI compiler trampoline we move x18 (temporary register - caller saved) to x19 (ETR, callee saved) before calling into native code, and restore it on the way back. Change-Id: If24091018d640027a497517a9238bf4a80d013aa Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
* ART: aarch64 jni compiler needs to extend small return typesAndreas Gampe2014-05-011-4/+18
| | | | | | | | | | | | | As aarch64 calling convention does not mandate extension on return values anymore and leaves the upper bits undefined, the jni compiler needs to sign- or zero-extend the returned values when necessary. As three architectures need extension now, refactor this fact into a flag into a virtual method. Add tests to JniTest that exercise the required extension. Change-Id: Idebb7c4dedebb852e58ade63e1c2b1eeced23104
* AArch64: Jni compiler fixesSerban Constantinescu2014-04-103-56/+108
| | | | | | | | | | | | | | | | | | | | | This patch fixes some of the issues with the ARM64 assembler and JNI compiler. The JNI compiler is not enabled by default, yet. To enable, change line 1884 in compiler/driver/compiler_driver.cc, removing kArm64 from the GenericJNI list. The compiler passes all tests in jni_compiler_test. Also change the common_compiler_test instruction-set-features logic. We allow tests when the build-time features are a subset of the runtime features. Dex2oat cross-compiling is now working. A 32b version of dex2oat should be able to compile correctly. Change-Id: I51d1c24f2c75d4397a11c54724a8b277ff3b3df8 Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
* AArch64: Fix Managed Register unit testsSerban Constantinescu2014-04-074-14/+171
| | | | | | | | Fixes the XZR change introduced by one of the previous patches. It also adds extra testing for VIXL register integration. Change-Id: I4935f06726e25829613ef7bb6ac052d82056812c Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
* Do not output ARM64 assembler debug code.Andreas Gampe2014-04-031-11/+0
| | | | | | | This breaks the run tests, which are a simple diff against an expected output. Please do such changes in a local change. Change-Id: Ib961919600ba79eca1356278bc6c09ca17041c7c
* Calling convention support for cross 64/32 compilation.Ian Rogers2014-04-011-5/+7
| | | | | | Add REX support for x86-64 operands. Change-Id: I093ae26fb8c111d54b8c72166f054984564c04c6
* Allow mixing of thread offsets between 32 and 64bit architectures.Ian Rogers2014-04-013-74/+66
| | | | | | | Begin a more full implementation x86-64 REX prefixes. Doesn't implement 64bit thread offset support for the JNI compiler. Change-Id: If9af2f08a1833c21ddb4b4077f9b03add1a05147
* x86_64: JNI compilerDmitry Petrochenko2014-03-282-2/+2
| | | | | | | | | | | Passed all tests from jni_compiler_test and art/test on host with jni_copiler. Incoming argument spill is enabled, entry_spills refactored. Now each entry spill contains data type size (4 or 8) and offset which should be used for spill. Assembler REX support implemented in opcodes used in JNI compiler. Please note, JNI compiler is not enabled by default yet (see compiler_driver.cc:1875). Change-Id: I5fd19cca72122b197aec07c3708b1e80c324be44 Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
* Trampoline and assembly fixes for ARM64Andreas Gampe2014-03-242-0/+12
| | | | | | | | | | | Trampolines need a jump, not a call. Expose br in the ARM64 assembler to allow this. The resolution trampoline is called with the Quick ABI, and will continue to a Quick ABI function. Then the method pointer must be in x0. Change-Id: I4e383b59d6c40a659d324a7faef3fadf0c890178
* Some more ARM64 tests that are invalid at the momentAndreas Gampe2014-03-191-4/+6
| | | | Change-Id: I7e5a3c093bb0b0fd04ef588946f8b843993f6d4e
* Parts of ARM64 should not be enabled, yetAndreas Gampe2014-03-191-4/+5
| | | | | | | The managed register test exercises tests that are supposed to hold in the final product, but the infrastructure is not at that point yet. Change-Id: I32bee942a13819620d9f6b1c0d9a8a14c9951764
* AArch64: Add arm64 runtime support.Stuart Monteith2014-03-192-1/+2
| | | | | | | | | Adds support for arm64 to ART. Assembler stubs are sufficient for down calls into interpreter. JNI compiler and generics are not finished. Basic Generic JNI functionality. Change-Id: I4a07c79d1e037b9f5746673480e32cf456867b82
* Enable annotalysis on clang ART builds.Ian Rogers2014-03-061-4/+4
| | | | | | | | | | | Fix clang build errors aswell as restructure locking/mutex code for correct thread safety analysis support. Reorder make dependencies so that host builds build first as they should provide better compilation errors than target. Remove host's use of -fno-omit-frame-pointer as it has no value with correct use of CFI, which we should have. Change-Id: I72cea8da9a3757b1a0b3acb4081feccb7c6cef90
* AArch64: Add ARM64 AssemblerSerban Constantinescu2014-03-056-0/+1890
This patch adds the ARM64 Assembler and ManagedRegister backend. The implementation of the Arm64Assembler class is based on VIXL (a programmatic A64 Assembler - see external/vixl ). Change-Id: I842fd574637a953c19631eedf26f6c70d9ed7f9e Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
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