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* Merge "ART: Move __memcmp16 from Bionic to ART"Andreas Gampe2014-06-101-1/+1
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| * ART: Move __memcmp16 from Bionic to ARTAndreas Gampe2014-06-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Handle __memcmp16 / MemCmp16 in ART. Import assembly implementations for arm and mips from Bionic. Use a generic C version for all other platforms. Removes the memcmp16 quick entrypoint, as it is never used. Bump the oat version and update thread.cc and checks to reflect the structural change. Change-Id: I54a5a1da2a0a43ef271c8aeda0bf2276b8b11ac6
* | Workaround frame size issues.Ian Rogers2014-06-101-1/+1
| | | | | | | | | | | | | | | | | | | | x86 and x86-64 are exceeding the frame size for the switch interpreter. The SOMETIMES_INLINE hack doesn't work with GCC as inline and the noinline attribute are mutually exclusive. As a temporary solution move the effected code to the the interpreter_common.cc file. Bug: 14882674 Change-Id: Id5383ef5436046b36565cd1d76de8e3d59f42cff
* | X86_64: Proper IMT fixMark Mendell2014-06-101-1/+2
|/ | | | | | | | | | | Unfortunately, 97184: X86_64: Pass 'hidden method index' in EAX wasn't correct. TargetReg(kInvokeTgt) is ALSO EAX, and so invoke-interface blows up, since the saved index is overwritten by the generated code. Change kInvokeTgt to EDI (the same as ARG0). Change-Id: I4b1d260237274ee26b9283d810d1b74484ea59af Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* Merge "Change MethodHelper to use a Handle."Mathieu Chartier2014-06-101-14/+13
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| * Change MethodHelper to use a Handle.Mathieu Chartier2014-06-091-14/+13
| | | | | | | | | | | | | | | | | | | | | | Added ConstHandle to help prevent errors where you modify the value stored in the handle of the caller. Also fixed compaction bugs related to not knowing MethodHelper::GetReturnType can resolve types. This bug was present in interpreter RETURN_OBJECT. Bug: 13077697 Change-Id: I71f964d4d810ab4debda1a09bc968af8f3c874a3
* | Merge "Round up arena allocations to 8 bytes."Vladimir Marko2014-06-104-4/+4
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| * | Round up arena allocations to 8 bytes.Vladimir Marko2014-06-104-4/+4
| | | | | | | | | | | | | | | | | | | | | Prevent SIGBUS/BUS_ADRALN when we use the arena for classes with 64-bit alignment. Change-Id: I5382ed7072fcfb2349f61558e1fd8257315ee336
* | | Remove TARGET_REX_SUPPORT define.Ian Rogers2014-06-102-52/+0
|/ / | | | | | | Change-Id: I1c3644176c101064261d13b50484d2e3ae456316
* | Plug code generator into liveness analysis.Nicolas Geoffray2014-06-1011-146/+376
| | | | | | | | | | | | Also implement spill slot support. Change-Id: If5e28811e9fbbf3842a258772c633318a2f4fafc
* | Merge "Add a type propagation phase after building SSA."Nicolas Geoffray2014-06-105-23/+160
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| * | Add a type propagation phase after building SSA.Nicolas Geoffray2014-06-095-23/+160
| | | | | | | | | | | | | | | | | | This ensures all phis have a type. Change-Id: I7e4f9a16d1efb5f64c493c1351749b352c870cbd
* | | Merge "X86_64: Pass 'hidden method index' in EAX"Ian Rogers2014-06-102-2/+2
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| * | | X86_64: Pass 'hidden method index' in EAXMark Mendell2014-06-092-2/+2
| | |/ | |/| | | | | | | | | | | | | | | | | | | Method* is in EDI, and EAX isn't an argument register, so EAX is free to hold the hidden method index. Change-Id: I793a54d00a4593e140f97144419d849b53bfdf44 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* | | Tidy up x86 assembler and fix byte register encoding.Ian Rogers2014-06-095-1503/+1561
| | | | | | | | | | | | | | | | | | | | | Also fix reg storage int size issues. Also fix bad use of byte registers in GenInlinedCas. Change-Id: Id47424f36f9000e051110553e0b51816910e2fe8
* | | Merge "X86_64: Fix core.oat compilation issues"Bill Buzbee2014-06-102-3/+8
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| * | | X86_64: Fix core.oat compilation issuesMark Mendell2014-06-092-3/+8
| | |/ | |/| | | | | | | | | | | | | | | | Fix neg-long and X86Mir2Lir::GenInstanceofFinal Change-Id: I7fbcc1a89857cc461f74b55573ac6cb7c8e64561 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* | | Merge "x86_64: Reduce dex2oat compilation logs"Bill Buzbee2014-06-101-1/+3
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| * | | x86_64: Reduce dex2oat compilation logsDmitry Petrochenko2014-06-101-1/+3
| |/ / | | | | | | | | | | | | | | | | | | Disable printing of all compiled methods to logcat. Change-Id: Ie210809f2595cc25da688a4ad0363c258bcf9233 Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
* | | Merge "AArch64: fix and enable sparse- and packed-switch."Bill Buzbee2014-06-103-9/+46
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| * | AArch64: fix and enable sparse- and packed-switch.Matteo Franchin2014-06-093-9/+46
| |/ | | | | | | | | | | | | | | Changed implementation of sparse- and packed-switch to use w and x registers appropriately. Also added a couple of utilities to obtain a w/s register corresponding to a given x/d register and viceversa. Change-Id: I485a110f6e91b09227d9e2a0b8b14224a10bca90
* | Merge "AArch64: Fix kOpLsl, rem-float/double."Bill Buzbee2014-06-093-5/+15
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| * AArch64: Fix kOpLsl, rem-float/double.Zheng Xu2014-06-093-5/+15
| | | | | | | | Change-Id: I6f7293493c0f94f96882d2e559e3eef659a23aec
* | Merge "Fix some bugs in graph construction/simplification methods."Nicolas Geoffray2014-06-098-35/+420
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| * Fix some bugs in graph construction/simplification methods.Nicolas Geoffray2014-06-098-35/+420
| | | | | | | | | | | | | | | | Also fix a brano during SSA construction. The code should not have been commented out. Added a test to cover what the code intends. Change-Id: Ia00ae79dcf75eb0d412f07649d73e7f94dbfb6f0
* | x86_64: Add long bytecode supports (2/2)Chao-ying Fu2014-06-075-130/+473
| | | | | | | | | | | | | | | | | | | | | | This patch adds implementation of math and complex long bytcodes, and basic long arithmetic. Change-Id: I811397d7e0ee8ad0d12b23d32ba58314d479d714 Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com> Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com> Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com> Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* | x86_64: Add long bytecode supports (1/2)Chao-ying Fu2014-06-077-145/+291
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch includes switch enabling and GenFillArray, assembler changes, updates of regalloc behavior for 64-bit, usage in basic utility operations, loading constants, and update for memory operations. Change-Id: I6d8aa35a75c5fd01d69c38a770c3398d0188cc8a Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com> Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com> Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com> Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* | Merge "x86_64: Hard Float ABI support in QCG"Bill Buzbee2014-06-0711-42/+714
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| * | x86_64: Hard Float ABI support in QCGDmitry Petrochenko2014-06-0711-42/+714
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch shows our efforts on resolving the ART limitations: - passing "float"/"double" arguments via FPR - passing "long" arguments via single GPR, not pair - passing more than 3 agruments via GPR. Work done: - Extended SpecialTargetRegister enum with kARG4, kARG5, fARG4..fARG7. - Created initial LoadArgRegs/GenDalvikX/FlushIns version in X86Mir2Lir. - Unlimited number of long/double/float arguments support - Refactored (v2) Change-Id: I5deadd320b4341d5b2f50ba6fa4a98031abc3902 Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com> Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com> Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com> Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* | | Merge "Change FieldHelper to use a handle."Mathieu Chartier2014-06-061-1/+3
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| * | | Change FieldHelper to use a handle.Mathieu Chartier2014-06-061-1/+3
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixed compaction bugs related to FieldHelper::GetType in: artSet32InstanceFromCode SetFieldValueImpl CheckReceiver Field_set interpreter::DoFieldPut MethodVerifier::VerifyISGet MethodVerifier::VerifyISPut MethodVerifier::VerifyIGetQuick Bug: 13077697 Change-Id: I7de9ded2893b5568d43e4daa86fd135bf5508b72
* | | Reduce header files including header files.Ian Rogers2014-06-066-0/+6
| |/ |/| | | | | | | | | Main focus is getting heap.h out of runtime.h. Change-Id: I8d13dce8512816db2820a27b24f5866cc871a04b
* | Merge "Use ScopedArenaVector instead of std::vector in SSA transformation."Vladimir Marko2014-06-062-2/+8
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| * | Use ScopedArenaVector instead of std::vector in SSA transformation.Vladimir Marko2014-06-062-2/+8
| | | | | | | | | | | | Change-Id: Ibf8471274f2d5e11fcc185044745434c3c82ed74
* | | Merge "Fixed and refactored profiler options handling"Calin Juravle2014-06-065-23/+34
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| * | | Fixed and refactored profiler options handlingCalin Juravle2014-06-065-23/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - extracted profiler options in a separate class - switched from system property reading to command line arguments - added profile based compilation options to CompilerOptions - removed no longer used kProfile compilation filter - optimize dex files only if the profiler is enabled - clean up unused arguments Bug: 12877748 Bug: 15275634 Change-Id: I37ff68e7694370950ce8db2360562e9058ecebb7
* | | | Merge "Clean up the sampling profiler"Calin Juravle2014-06-062-25/+14
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| * | Clean up the sampling profilerCalin Juravle2014-06-062-25/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - rename variables/fields names to match the code style (use _underscore_names_) - extract common property parsing in utils.cc - fail to load profile file if any line is malformed - added ProfileFile to manage the profile data generate in the previous runs (replaces ProfileHelper and nests ProfileData) Bug: 12877748 Change-Id: Ie7bda30bfdeb7e78534c986615b0649eac12a97b
* | | Add an optimization for removing redundant suspend tests in ARTWei Jin2014-06-056-10/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL: (1) eliminates redundant suspend checks (dominated by another check), (2) removes the special treatment of the R4 register, which got reset on every native call, possibly yielding long execution sequences without any suspend checks, and (3) fixes the absence of suspend checks in leaf methods. (2) and (3) increase the frequency of suspend checks, which improves the performance of GC and the accuracy of profile data. To compensate for the increased number of checks, we implemented an optimization that leverages dominance information to remove redundant suspend checks on back edges. Based on the results of running the Caffeine benchmark on Nexus 7, the patch performs roughly 30% more useful suspend checks, spreading them much more evenly along the execution trace, while incurring less than 1% overhead. For flexibility consideration, this CL defines two flags to control the enabling of optimizations. The original implementation is the default. Change-Id: I31e81a5b3c53030444dbe0434157274c9ab8640f Signed-off-by: Wei Jin <wejin@google.com>
* | | Remove unused variable in assembler test.Dave Allison2014-06-051-0/+2
| | | | | | | | | | | | | | | | | | This is flagged as an error when building master, but not others... Change-Id: Iaea5307b06d8e4fa1a9d1035905fc204eb98559a
* | | Fix assembler test to use path if it can't find tools.Dave Allison2014-06-051-7/+7
| | | | | | | | | | | | | | | | | | This fixes build breakage. Change-Id: I8074d47f1c1470cf886d517e9e68a6a6b4330485
* | | Merge "Thumb2 assembler for JNI compiler and optimizing compiler"Dave Allison2014-06-0515-1653/+11537
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| * | Thumb2 assembler for JNI compiler and optimizing compilerDave Allison2014-06-0515-1653/+11537
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This provides a programmatic assembler for the thumb2 instruction set for ARM. The interface is the same as the ARM assembler and the ARM assembler has been moved into Arm32Assembler. The assembler handles most 16 and 32 bit instructions and also allows relocations due to branch expansion. It will also rewrite cbz/cbnz instructions if they go out of range. It also changes the JNI compiler to use the thumb2 assembler as opposed to forcing it to use ARM32. The trampoline compiler still uses ARM due to the way it returns the address of its generated code. A trampoline in thumb2 is the same size as that in ARM anyway (8 bytes). Provides gtest for testing the thumb2 instruction output. This gtest only runs on the host as it uses arm-eabi-objdump to disassemble the generated code. On the target the output is not checked but the assembler will still be run to perform all its checks. Change-Id: Icd9742b6f13541bec5b23097896727392e3a6fb6
* | | Merge "Use std::enable_if instead of a custom helper class."Vladimir Marko2014-06-051-18/+7
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| * | | Use std::enable_if instead of a custom helper class.Vladimir Marko2014-06-051-18/+7
| | | | | | | | | | | | | | | | Change-Id: Iffa0f0350ccc4fce698b9a16aefd340e16654076
* | | | x86_64: Turn on 64-bit core registers initialization.Dmitry Petrochenko2014-06-051-6/+24
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables 64-bit core registers initialization for x86_64. The backend update with 64-bit temp support is in progress. Change-Id: If7c9a62c1145f81050adda86f2beed427220baa2 Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com> Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com> Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com> Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* | | Avoid register pool allocations on the heap.Vladimir Marko2014-06-057-154/+296
| | | | | | | | | | | | | | | | | | | | | | | | Create a helper template class ArrayRef and use it instead of std::vector<> for register pools in target_<arch>.cc to avoid these heap allocations during program startup. Change-Id: I4ab0205af9c1d28a239c0a105fcdc60ba800a70a
* | | Merge "AArch64: Fix cmp-long and method with long arguments."Bill Buzbee2014-06-043-18/+12
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| * | | AArch64: Fix cmp-long and method with long arguments.Zheng Xu2014-06-043-18/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Fix cmp-long. 2. Use single register to pass long argument. 3. Flush StackReference<ArtMethod> on arm64 the same as in common code. 3. Fix the mismatch in calculate reg offset. Change-Id: Ie2723260fb143512e4da6ee88d4f3aded80d3d5e
* | | | ART: Make LOCAL_CLANG architecture dependent for the targetAndreas Gampe2014-06-041-18/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Be selective for which target we compile with Clang. Currently we only want to compile with Clang for ARM64, which means we need to be careful about ARM, which is the second architecture for that. Bug: 15014252 (cherry picked from commit 9689e3768621130b2536564f4e00fcb6b3d25df4) Change-Id: I312e1caea08f2f3a20304b27f979d3c7b72b0a04
generated by cgit v1.1 at 2024-09-18 16:54:31 +0000