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* Vixl: Update the VIXL interface to VIXL 1.7 and enable VIXL debug.Serban Constantinescu2014-11-282-2/+6
| | | | | | | | This patch updates the interface to VIXL 1.7 and enables the debug version of VIXL when ART is built in debug mode. Change-Id: I443fb941bec3cffefba7038f93bb972e6b7d8db5 Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
* Merge "Improvements to the ARM64 disassembler."Ian Rogers2014-11-193-5/+115
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| * Improvements to the ARM64 disassembler.Alexandre Rames2014-10-293-5/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This contains three changes: - Use register aliases in the disassembly. - When loading from a literal pool, show what is being loaded. - Disassemble using absolute addresses on ARM64. This ensures that addresses disassembled are coherent with instruction location addresses shown. Examples of disassembled instructions before and after the changes: Before: movz w17, #0x471f ldr d9, pc+736 (addr 0x72690d50) After: movz wip1, #0x471f ldr d9, pc+736 (addr 0x72690d50) (-745.133) Change-Id: I72fdc160fac26f74126921834f17a581c26fd5d8
* | Revert "Arm64: Use the debug version of VIXL for debug builds."Nicolas Geoffray2014-11-171-5/+1
| | | | | | | | | | | | This reverts commit 195c576fbff290d4c313b67ed24ca36f2531acc4. Change-Id: Id992a43ae346bb4c38a6c47639b02aea838d974a
* | Arm64: Use the debug version of VIXL for debug builds.Serban Constantinescu2014-11-141-1/+5
| | | | | | | | | | | | | | | | This patch builds the debug version of ART against VIXL debug. In this way VIXL will assert misuses of the assembler and disassembler. Change-Id: Ic4654eb20e420f23b40e96a69be452dc50770c1c Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
* | Instruction set features for ARM64, MIPS and X86.Ian Rogers2014-11-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Also, refactor how feature strings are handled so they are additive or subtractive. Make MIPS have features for FPU 32-bit and MIPS v2. Use in the quick compiler rather than #ifdefs that wouldn't have worked in cross-compilation. Add SIMD features for x86/x86-64 proposed in: https://android-review.googlesource.com/#/c/112370/ Bug: 18056890 Change-Id: Ic88ff84a714926bd277beb74a430c5c7d5ed7666
* | Tidy x86 disassemblerIan Rogers2014-11-071-24/+84
| | | | | | | | Change-Id: I2f0a2851a15f5a099a5bc0249e3ea0616cdcd94e
* | ART: More warningsAndreas Gampe2014-11-042-44/+8
| | | | | | | | | | | | | | Enable -Wno-conversion-null, -Wredundant-decls and -Wshadow in general, and -Wunused-but-set-parameter for GCC builds. Change-Id: I81bbdd762213444673c65d85edae594a523836e5
* | Tidy and reduce ART library dependencies on the host.Ian Rogers2014-10-301-2/+2
|/ | | | | | | Move to shared rather than static libraries. Avoids capture of all static libraries library dependencies. Change-Id: I2be96e92dad4ed1842d76b044745f2a2e15372eb
* Tidy logging code not using UNIMPLEMENTED.Ian Rogers2014-10-241-2/+2
| | | | Change-Id: I7a79c1671a6ff8b2040887133b3e0925ef9a3cfe
* C++11 related clean-up of DISALLOW_..Ian Rogers2014-10-225-6/+7
| | | | | | | | | | | | | | | | | | Move DISALLOW_COPY_AND_ASSIGN to delete functions. By no having declarations with no definitions this prompts better warning messages so deal with these by correcting the code. Add a DISALLOW_ALLOCATION and use for ValueObject and mirror::Object. Make X86 assembly operand types ValueObjects to fix compilation errors. Tidy the use of iostream and ostream. Avoid making cutils a dependency via mutex-inl.h for tests that link against libart. Push tracing dependencies into appropriate files and mutex.cc. x86 32-bit host symbols size is increased for libarttest, avoid copying this in run-test 115 by using symlinks and remove this test's higher than normal ulimit. Fix the RunningOnValgrind test in RosAllocSpace to not use GetHeap as it returns NULL when the heap is under construction by Runtime. Change-Id: Ia246f7ac0c11f73072b30d70566a196e9b78472b
* Tidy up logging.Ian Rogers2014-10-223-0/+3
| | | | | | | | | | | | | | | | | Move gVerboseMethods to CompilerOptions. Now "--verbose-methods=" option to dex2oat rather than runtime argument "-verbose-methods:". Move ToStr and Dumpable out of logging.h, move LogMessageData into logging.cc except for a forward declaration. Remove ConstDumpable as Dump methods are all const (and make this so if not currently true). Make LogSeverity an enum and improve compile time assertions and type checking. Remove log_severity.h that's only used in logging.h. With system headers gone from logging.h, go add to .cc files missing system header includes. Also, make operator new in ValueObject private for compile time instantiation checking. Change-Id: I3228f614500ccc9b14b49c72b9821c8b0db3d641
* Make ART compile with GCC -O0 again.Ian Rogers2014-10-161-0/+1
| | | | | | | | | | | | | Tidy up InstructionSetFeatures so that it has a type hierarchy dependent on architecture. Add to instruction_set_test to warn when InstructionSetFeatures don't agree with ones from system properties, AT_HWCAP and /proc/cpuinfo. Clean-up class linker entry point logic to not return entry points but to test whether the passed code is the particular entrypoint. This works around image trampolines that replicate entrypoints. Bug: 17993736 Change-Id: I5f4b49e88c3b02a79f9bee04f83395146ed7be23
* ART: ARM64: Fix instruction addresses in the disassembly.Alexandre Rames2014-10-131-7/+3
| | | | Change-Id: Ic8b6e0d5cd15e029de9bc82e0a4fc2e33d07936c
* Enable -Wimplicit-fallthrough.Ian Rogers2014-10-092-6/+7
| | | | | | | | Falling through switch cases on a clang build must now annotate the fallthrough with the FALLTHROUGH_INTENDED macro. Bug: 17731372 Change-Id: I836451cd5f96b01d1ababdbf9eef677fe8fa8324
* ART: Fix some -Wpedantic errorsAndreas Gampe2014-09-292-14/+14
| | | | | | | | | | | | | | | | Remove extra semicolons. Dollar signs in C++ identifiers are an extension. Named variadic macros are an extension. Binary literals are a C++14 feature. Enum re-declarations are not allowed. Overflow. Change-Id: I7d16b2217b2ef2959ca69de84eaecc754517714a
* Avoid printing absolute addresses in oatdumpBrian Carlstrom2014-09-1610-32/+75
| | | | | | | | | | | | | | | | | - Added printing of OatClass offsets. - Added printing of OatMethod offsets. - Added bounds checks for code size size, code size, mapping table, gc map, vmap table. - Added sanity check of 100k for code size. - Added partial disassembly of questionable code. - Added --no-disassemble to disable disassembly. - Added --no-dump:vmap to disable vmap dumping. - Reordered OatMethod info to be in file order. Bug: 15567083 (cherry picked from commit 34fa79ece5b3a1940d412cd94dbdcc4225aae72f) Change-Id: I2c368f3b81af53b735149a866f3e491c9ac33fb8
* ART: Vectorization opcode implementation fixesLupusoru, Razvan A2014-09-031-59/+34
| | | | | | | | | This patch fixes the implementation of the x86 vectorization opcodes. Change-Id: I0028d54a9fa6edce791b7e3a053002d076798748 Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com> Signed-off-by: Udayan Banerji <udayan.banerji@intel.com> Signed-off-by: Philbert Lin <philbert.lin@intel.com>
* ART: Add non-temporal store supportJean Christophe Beyler2014-08-261-0/+1
| | | | | | | | | | | Added non-temporal store support as a hint from the ME. Added the implementation of the memory barrier extended instruction that supports non-temporal stores by explicitly serializing all previous store-to-memory instructions. Change-Id: I8205a92083f9725253d8ce893671a133a0b6849d Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com> Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
* Implement inlined shift long for 32bitYixin Shou2014-08-141-0/+12
| | | | | | | Added support for x86 inlined shift long for 32bit Change-Id: I6caef60dd7d80227c3057fd6f64b0ecb11025afa Signed-off-by: Yixin Shou <yixin.shou@intel.com>
* Fix art build scriptJunmo Park2014-08-131-2/+2
| | | | | | | Use ART_BUILD_HOST_NDEBUG instead of ART_BUILD_NDEBUG. Change-Id: I0ff590552f47d3354287a155b51936a7aef82f1f Signed-off-by: Junmo Park <junmoz.park@samsung.com>
* ART: Correct disassembling of 64bit immediates on x86_64Vladimir Kostyukov2014-07-301-2/+2
| | | | | | | | | The patch fixes an issue with disassembling 'movsxd' and 'movabsq' instructions altered with 64bit immediates: not only a REX.W prefix may be prepended to these instructions. Change-Id: Ida7c7b368327a6b5cae1ff12ec00ceb0769c0a3d Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
* Implement array get and array put in optimizing.Nicolas Geoffray2014-07-282-8/+44
| | | | | | Also fix a couple of assembler/disassembler issues. Change-Id: I705c8572988c1a9c4df3172b304678529636d5f6
* ART: Correct disassembling of regs from opcodesVladimir Kostyukov2014-07-091-3/+5
| | | | | | | | | | | | | | | | Registers, which are part of opcode might have 1-byte size or 2-byte size depending on the instruction and 66h prefix. This patch makes the decoding of such instruction correct. Examples: - '664155' should be decoded as 'push r13w' (66h + REX.B) - '41B320' should be decoded as 'mov r11l, 0x20' (byte-operand + REX.B) Change-Id: I83913e3a5f2ef03c4019c0f5eea6b11fc51ee4cc Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
* Merge "X86 Backend support for vectorized float and byte 16x16 operations"Ian Rogers2014-07-081-3/+17
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| * X86 Backend support for vectorized float and byte 16x16 operationsUdayan Banerji2014-07-081-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support for reserving vector registers for the duration of vector loop. Add support for 16x16 multiplication, shifts, and add reduce. Changed the vectorization implementation to be able to use the dataflow elements for SSA recreation and fixed a few implementation details. Change-Id: I2f358f05f574fc4ab299d9497517b9906f234b98 Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com> Signed-off-by: Olivier Come <olivier.come@intel.com> Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
* | x86_64: Clean-up after cmp-long fixSerguei Katkov2014-07-091-4/+6
|/ | | | | | | | The patch adresses the coments from review done by Ian Rogers. Clean-up of assembler. Change-Id: I9dbb350dfc6645f8a63d624b2b785233529459a9 Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
* Merge "ART: Add HADDPS/HADDPD/SHUFPS/SHUFPD instruction generation"Ian Rogers2014-07-071-0/+27
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| * ART: Add HADDPS/HADDPD/SHUFPS/SHUFPD instruction generationOlivier Come2014-06-251-0/+27
| | | | | | | | | | | | | | | | The patch adds the HADDPS, HADDPD, SHUFPS, and SHUFPD instruction generation for X86. Change-Id: Ida105d3e57be231a5331564c1a9bc298cf176ce6 Signed-off-by: Olivier Come <olivier.come@intel.com>
* | ART: FF-opcodes are target-specificVladimir Kostyukov2014-07-031-8/+15
| | | | | | | | | | | | | | | | | | Some of the FF-opcodes' (i.e., push, call, jmp) register names depend on the the target (32-bit vs 64-bit). This patch makes such opcodes target-specific. Change-Id: I4fa0b7ee5310e14f4022850ac2160c21be5d1c99 Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
* | Load 64 bit constant into GPR by single instruction for 64bit modeYixin Shou2014-07-021-2/+12
| | | | | | | | | | | | | | | | | | This patch load 64 bit constant into a register by a single movabsq instruction on 64 bit bit instead of previous mov, shift, add instruction sequences. Change-Id: I9d013c4f6c0b5c2e43bd125f91436263c7e6028c Signed-off-by: Yixin Shou <yixin.shou@intel.com>
* | ART: FPU instructions support in disassemblerVladimir Kostyukov2014-07-011-5/+27
|/ | | | | | | | | | This patch extends the disassembler with new FPU instructions: - fstsw - fucompp - fprem Change-Id: I9458510bc17f2b3b286edec102552f64be05147e Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
* Multilib ART host.Ian Rogers2014-06-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Build ART for the host as a multilib project with dalvikvm32 and dalvikvm64 running as 32 or 64-bit repsectfully. Note, currently multilib host builds are not the default, you make the so by setting BUILD_HOST_64bit=1. Extend tests to execute in both 32 and 64-bit modes. By default both 32 and 64-bit tests are run, add 32 or 64 to the end of a test name to run it in purely that flavor. Given the extra spam, modify oat tests to only generate console output when the test fails. Change the test harness so that common commands are run when a test should be skipped, when it passes or when it fails. Use these commands to generate a summary of passing, skipped and failing tests. Tests will be skipped if they are known to be broken or if a test has already failed. Setting the variable TEST_ART_KEEP_GOING=true will force working tests not to be skipped. In this change all tests running on the optimizing compiler are marked broken due to breakages running them in a multilib environment. Break apart Android.common.mk into its constituent parts, along with other pieces of reorganization. Stylistic nit, we refer to make rule targets as targets thereby overloading the term target. While consistent with make's terminology, its confusing with the Android notion of target. I've switched to just calling targets rules to avoid confusion in host tests. Change-Id: I5190fc3de46800a949fbb06b3f4c258ca89ccde9
* Add some more instruction support to optimizing compiler.Dave Allison2014-06-241-15/+54
| | | | | | | | | | | | | | | This adds a few more DEX instructions to the optimizing compiler's builder (constants, moves, if_xx, etc). Also: * Changes the codegen for IF_XX instructions to use a condition rather than comparing a value against 0. * Fixes some instructions in the ARM disassembler. * Fixes PushList and PopList in the thumb2 assembler. * Switches the assembler for the optimizing compiler to thumb2 rather than ARM. Change-Id: Iaafcd02243ccc5b03a054ef7a15285b84c06740f
* X86 Dis: Add missing mov byte; Add size suffixesMark Mendell2014-06-211-6/+32
| | | | | | | | | Yet another instruction not disassembled properly. Add 'b', 'w', 'q' to opcodes to diffferentiate between various versions and make it more understandable. Change-Id: Ib794aac660bc8bc4900bfa49eab5aed682996adc Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* Remove deprecated WITH_HOST_DALVIK.Ian Rogers2014-06-101-8/+6
| | | | | | | | | | | | | | | | | | | | | | | Bug: 13751317 Fix the Mac build: - disable x86 selector removal that causes OS/X 10.9 kernel panics, - madvise don't need does zero memory on the Mac, factor into MemMap routine, - switch to the elf.h in elfutils to avoid Linux kernel dependencies, - we can't rely on exclusive_owner_ being available from other pthread libraries so maintain our own when futexes aren't available (we can't rely on the OS/X 10.8 hack any more), - fix symbol naming in assembly code, - work around C library differences, - disable backtrace in DumpNativeStack to avoid a broken libbacktrace dependency, - disable main thread signal handling logic, - align the stack in stub_test, - use $(HOST_SHLIB_SUFFIX) rather than .so in host make file variables. Not all host tests are passing on the Mac with this change. dex2oat works as does running HelloWorld. Change-Id: I5a232aedfb2028524d49daa6397a8e60f3ee40d3
* Add Move with Sign Extend Double to disassemblerMark Mendell2014-06-081-0/+11
| | | | | | | I noticed another missing instruction. Change-Id: I71170496b014ac2609116eff2aeb13a13e71e263 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* Fix X86 disassambler printing of XMM, MM registersMark Mendell2014-06-051-1/+1
| | | | | | | Printing of uint8_t is done as a char, rather than an integer. Change-Id: I996e7d7dd902695be6366ab816fea65b675c2ad9 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* Merge "ART: x86_64 disassembler improvements"Ian Rogers2014-06-041-21/+68
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| * ART: x86_64 disassembler improvementsVladimir Kostyukov2014-06-041-21/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch (a) enables full support of 64bit extended regs r8-r15, including 8bit r8l-r15l, 16bit r8w-r15w and also 32bit r8d-r15d (b) fixes an issue with decoding reg from ModRM byte (REX.B should be used) (c) fixes an issue with decoding regs from SIB byte (regs that contain addr are target-specific) Change-Id: I6bf3d7102780907b1cbe2a46927352ac0b506295 Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
* | ART: Make LOCAL_CLANG architecture dependent for the targetAndreas Gampe2014-06-041-12/+7
|/ | | | | | | | | | | | Be selective for which target we compile with Clang. Currently we only want to compile with Clang for ARM64, which means we need to be careful about ARM, which is the second architecture for that. Bug: 15014252 (cherry picked from commit 9689e3768621130b2536564f4e00fcb6b3d25df4) Change-Id: I312e1caea08f2f3a20304b27f979d3c7b72b0a04
* Support disassembly of 16-bit immediatesMark Mendell2014-05-301-2/+7
| | | | | Change-Id: I66f5ce93077241204311e52c547599f5287bae04 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* Implement all vector instructions for X86Mark Mendell2014-05-241-4/+193
| | | | | | | | Add X86 code generation for the vector operations. Added support for X86 disassembler for the new instructions. Change-Id: I72b48f5efa3a516a16bb1dd4bdb5c9270a8db53a Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* Move art host to libc++Dan Albert2014-05-211-1/+1
| | | | Change-Id: Ia51a4fdfdbae7377130a43c401c2d8d241671d1e
* Now we have a proper C++ library, use std::unique_ptr.Ian Rogers2014-05-191-1/+1
| | | | | | | Also remove the Android.libcxx.mk and other bits of stlport compatibility mechanics. Change-Id: Icdf7188ba3c79cdf5617672c1cfd0a68ae596a61
* Fix a few 64-bit compilation of 32-bit code issues.Ian Rogers2014-05-011-3/+3
| | | | | | Bug: 13423943 Change-Id: I939389413af0a68c0d95b23cd598b7c42afa4383
* ART: Enables x86_64 disassemblyVladimir Kostyukov2014-04-251-7/+25
| | | | | | | | | This patch (a) cuts a REX prefix from the instruction and (b) adds missed 32bit disp to instructions with ModR/M and SIB bytes. Change-Id: I2674678224ca27746b33d4006ed38d497972309f Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
* Merge "ART: Fixes an issue with REX prefix for instructions with no ModRM byte"Ian Rogers2014-04-241-1/+1
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| * ART: Fixes an issue with REX prefix for instructions with no ModRM byteVladimir Kostyukov2014-04-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are instructions (such as push, pop, mov) in the x86 ISA that encode first operands in their opcodes (opcode + reg). In order to enable an extended 64bit registers (R9-R15) a special prefix REX.B should be emitted before such instructions. This patch fixes the issue when REX.R prefix was emitted before instructions with no MorRM byte. So, the REX-prefix was simply ignored by CPU for those instructions whose operands are encoded in their opcodes. This patch makes the jni_compiler_test passed with JNI compiler enabled for x86_64 target. Change-Id: Ib84da1cf9f8ff96bd7afd4e0fc53078f3231f8ec Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
* | Preparation for transition to libc++.Ian Rogers2014-04-161-4/+3
|/ | | | | | | Move the dependency on libc++ to its own makefile so that we can switch in a single place between libc++ and stlport. Change-Id: Ie61e7d054dcd049e36d5e7298c27d8a4abe6edf7
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