summaryrefslogtreecommitdiffstats
path: root/disassembler
Commit message (Collapse)AuthorAgeFilesLines
...
* Implement inlined shift long for 32bitYixin Shou2014-08-141-0/+12
| | | | | | | Added support for x86 inlined shift long for 32bit Change-Id: I6caef60dd7d80227c3057fd6f64b0ecb11025afa Signed-off-by: Yixin Shou <yixin.shou@intel.com>
* Fix art build scriptJunmo Park2014-08-131-2/+2
| | | | | | | Use ART_BUILD_HOST_NDEBUG instead of ART_BUILD_NDEBUG. Change-Id: I0ff590552f47d3354287a155b51936a7aef82f1f Signed-off-by: Junmo Park <junmoz.park@samsung.com>
* ART: Correct disassembling of 64bit immediates on x86_64Vladimir Kostyukov2014-07-301-2/+2
| | | | | | | | | The patch fixes an issue with disassembling 'movsxd' and 'movabsq' instructions altered with 64bit immediates: not only a REX.W prefix may be prepended to these instructions. Change-Id: Ida7c7b368327a6b5cae1ff12ec00ceb0769c0a3d Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
* Implement array get and array put in optimizing.Nicolas Geoffray2014-07-282-8/+44
| | | | | | Also fix a couple of assembler/disassembler issues. Change-Id: I705c8572988c1a9c4df3172b304678529636d5f6
* ART: Correct disassembling of regs from opcodesVladimir Kostyukov2014-07-091-3/+5
| | | | | | | | | | | | | | | | Registers, which are part of opcode might have 1-byte size or 2-byte size depending on the instruction and 66h prefix. This patch makes the decoding of such instruction correct. Examples: - '664155' should be decoded as 'push r13w' (66h + REX.B) - '41B320' should be decoded as 'mov r11l, 0x20' (byte-operand + REX.B) Change-Id: I83913e3a5f2ef03c4019c0f5eea6b11fc51ee4cc Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
* Merge "X86 Backend support for vectorized float and byte 16x16 operations"Ian Rogers2014-07-081-3/+17
|\
| * X86 Backend support for vectorized float and byte 16x16 operationsUdayan Banerji2014-07-081-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support for reserving vector registers for the duration of vector loop. Add support for 16x16 multiplication, shifts, and add reduce. Changed the vectorization implementation to be able to use the dataflow elements for SSA recreation and fixed a few implementation details. Change-Id: I2f358f05f574fc4ab299d9497517b9906f234b98 Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com> Signed-off-by: Olivier Come <olivier.come@intel.com> Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
* | x86_64: Clean-up after cmp-long fixSerguei Katkov2014-07-091-4/+6
|/ | | | | | | | The patch adresses the coments from review done by Ian Rogers. Clean-up of assembler. Change-Id: I9dbb350dfc6645f8a63d624b2b785233529459a9 Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
* Merge "ART: Add HADDPS/HADDPD/SHUFPS/SHUFPD instruction generation"Ian Rogers2014-07-071-0/+27
|\
| * ART: Add HADDPS/HADDPD/SHUFPS/SHUFPD instruction generationOlivier Come2014-06-251-0/+27
| | | | | | | | | | | | | | | | The patch adds the HADDPS, HADDPD, SHUFPS, and SHUFPD instruction generation for X86. Change-Id: Ida105d3e57be231a5331564c1a9bc298cf176ce6 Signed-off-by: Olivier Come <olivier.come@intel.com>
* | ART: FF-opcodes are target-specificVladimir Kostyukov2014-07-031-8/+15
| | | | | | | | | | | | | | | | | | Some of the FF-opcodes' (i.e., push, call, jmp) register names depend on the the target (32-bit vs 64-bit). This patch makes such opcodes target-specific. Change-Id: I4fa0b7ee5310e14f4022850ac2160c21be5d1c99 Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
* | Load 64 bit constant into GPR by single instruction for 64bit modeYixin Shou2014-07-021-2/+12
| | | | | | | | | | | | | | | | | | This patch load 64 bit constant into a register by a single movabsq instruction on 64 bit bit instead of previous mov, shift, add instruction sequences. Change-Id: I9d013c4f6c0b5c2e43bd125f91436263c7e6028c Signed-off-by: Yixin Shou <yixin.shou@intel.com>
* | ART: FPU instructions support in disassemblerVladimir Kostyukov2014-07-011-5/+27
|/ | | | | | | | | | This patch extends the disassembler with new FPU instructions: - fstsw - fucompp - fprem Change-Id: I9458510bc17f2b3b286edec102552f64be05147e Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
* Multilib ART host.Ian Rogers2014-06-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Build ART for the host as a multilib project with dalvikvm32 and dalvikvm64 running as 32 or 64-bit repsectfully. Note, currently multilib host builds are not the default, you make the so by setting BUILD_HOST_64bit=1. Extend tests to execute in both 32 and 64-bit modes. By default both 32 and 64-bit tests are run, add 32 or 64 to the end of a test name to run it in purely that flavor. Given the extra spam, modify oat tests to only generate console output when the test fails. Change the test harness so that common commands are run when a test should be skipped, when it passes or when it fails. Use these commands to generate a summary of passing, skipped and failing tests. Tests will be skipped if they are known to be broken or if a test has already failed. Setting the variable TEST_ART_KEEP_GOING=true will force working tests not to be skipped. In this change all tests running on the optimizing compiler are marked broken due to breakages running them in a multilib environment. Break apart Android.common.mk into its constituent parts, along with other pieces of reorganization. Stylistic nit, we refer to make rule targets as targets thereby overloading the term target. While consistent with make's terminology, its confusing with the Android notion of target. I've switched to just calling targets rules to avoid confusion in host tests. Change-Id: I5190fc3de46800a949fbb06b3f4c258ca89ccde9
* Add some more instruction support to optimizing compiler.Dave Allison2014-06-241-15/+54
| | | | | | | | | | | | | | | This adds a few more DEX instructions to the optimizing compiler's builder (constants, moves, if_xx, etc). Also: * Changes the codegen for IF_XX instructions to use a condition rather than comparing a value against 0. * Fixes some instructions in the ARM disassembler. * Fixes PushList and PopList in the thumb2 assembler. * Switches the assembler for the optimizing compiler to thumb2 rather than ARM. Change-Id: Iaafcd02243ccc5b03a054ef7a15285b84c06740f
* X86 Dis: Add missing mov byte; Add size suffixesMark Mendell2014-06-211-6/+32
| | | | | | | | | Yet another instruction not disassembled properly. Add 'b', 'w', 'q' to opcodes to diffferentiate between various versions and make it more understandable. Change-Id: Ib794aac660bc8bc4900bfa49eab5aed682996adc Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* Remove deprecated WITH_HOST_DALVIK.Ian Rogers2014-06-101-8/+6
| | | | | | | | | | | | | | | | | | | | | | | Bug: 13751317 Fix the Mac build: - disable x86 selector removal that causes OS/X 10.9 kernel panics, - madvise don't need does zero memory on the Mac, factor into MemMap routine, - switch to the elf.h in elfutils to avoid Linux kernel dependencies, - we can't rely on exclusive_owner_ being available from other pthread libraries so maintain our own when futexes aren't available (we can't rely on the OS/X 10.8 hack any more), - fix symbol naming in assembly code, - work around C library differences, - disable backtrace in DumpNativeStack to avoid a broken libbacktrace dependency, - disable main thread signal handling logic, - align the stack in stub_test, - use $(HOST_SHLIB_SUFFIX) rather than .so in host make file variables. Not all host tests are passing on the Mac with this change. dex2oat works as does running HelloWorld. Change-Id: I5a232aedfb2028524d49daa6397a8e60f3ee40d3
* Add Move with Sign Extend Double to disassemblerMark Mendell2014-06-081-0/+11
| | | | | | | I noticed another missing instruction. Change-Id: I71170496b014ac2609116eff2aeb13a13e71e263 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* Fix X86 disassambler printing of XMM, MM registersMark Mendell2014-06-051-1/+1
| | | | | | | Printing of uint8_t is done as a char, rather than an integer. Change-Id: I996e7d7dd902695be6366ab816fea65b675c2ad9 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* Merge "ART: x86_64 disassembler improvements"Ian Rogers2014-06-041-21/+68
|\
| * ART: x86_64 disassembler improvementsVladimir Kostyukov2014-06-041-21/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch (a) enables full support of 64bit extended regs r8-r15, including 8bit r8l-r15l, 16bit r8w-r15w and also 32bit r8d-r15d (b) fixes an issue with decoding reg from ModRM byte (REX.B should be used) (c) fixes an issue with decoding regs from SIB byte (regs that contain addr are target-specific) Change-Id: I6bf3d7102780907b1cbe2a46927352ac0b506295 Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
* | ART: Make LOCAL_CLANG architecture dependent for the targetAndreas Gampe2014-06-041-12/+7
|/ | | | | | | | | | | | Be selective for which target we compile with Clang. Currently we only want to compile with Clang for ARM64, which means we need to be careful about ARM, which is the second architecture for that. Bug: 15014252 (cherry picked from commit 9689e3768621130b2536564f4e00fcb6b3d25df4) Change-Id: I312e1caea08f2f3a20304b27f979d3c7b72b0a04
* Support disassembly of 16-bit immediatesMark Mendell2014-05-301-2/+7
| | | | | Change-Id: I66f5ce93077241204311e52c547599f5287bae04 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* Implement all vector instructions for X86Mark Mendell2014-05-241-4/+193
| | | | | | | | Add X86 code generation for the vector operations. Added support for X86 disassembler for the new instructions. Change-Id: I72b48f5efa3a516a16bb1dd4bdb5c9270a8db53a Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* Move art host to libc++Dan Albert2014-05-211-1/+1
| | | | Change-Id: Ia51a4fdfdbae7377130a43c401c2d8d241671d1e
* Now we have a proper C++ library, use std::unique_ptr.Ian Rogers2014-05-191-1/+1
| | | | | | | Also remove the Android.libcxx.mk and other bits of stlport compatibility mechanics. Change-Id: Icdf7188ba3c79cdf5617672c1cfd0a68ae596a61
* Fix a few 64-bit compilation of 32-bit code issues.Ian Rogers2014-05-011-3/+3
| | | | | | Bug: 13423943 Change-Id: I939389413af0a68c0d95b23cd598b7c42afa4383
* ART: Enables x86_64 disassemblyVladimir Kostyukov2014-04-251-7/+25
| | | | | | | | | This patch (a) cuts a REX prefix from the instruction and (b) adds missed 32bit disp to instructions with ModR/M and SIB bytes. Change-Id: I2674678224ca27746b33d4006ed38d497972309f Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
* Merge "ART: Fixes an issue with REX prefix for instructions with no ModRM byte"Ian Rogers2014-04-241-1/+1
|\
| * ART: Fixes an issue with REX prefix for instructions with no ModRM byteVladimir Kostyukov2014-04-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are instructions (such as push, pop, mov) in the x86 ISA that encode first operands in their opcodes (opcode + reg). In order to enable an extended 64bit registers (R9-R15) a special prefix REX.B should be emitted before such instructions. This patch fixes the issue when REX.R prefix was emitted before instructions with no MorRM byte. So, the REX-prefix was simply ignored by CPU for those instructions whose operands are encoded in their opcodes. This patch makes the jni_compiler_test passed with JNI compiler enabled for x86_64 target. Change-Id: Ib84da1cf9f8ff96bd7afd4e0fc53078f3231f8ec Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
* | Preparation for transition to libc++.Ian Rogers2014-04-161-4/+3
|/ | | | | | | Move the dependency on libc++ to its own makefile so that we can switch in a single place between libc++ and stlport. Change-Id: Ie61e7d054dcd049e36d5e7298c27d8a4abe6edf7
* Revert "Revert "Revert "Use trampolines for calls to helpers"""Dave Allison2014-04-091-25/+5
| | | | | | This reverts commit f9487c039efb4112616d438593a2ab02792e0304. Change-Id: Id48a4aae4ecce73db468587967968a3f7618b700
* Revert "Revert "Use trampolines for calls to helpers""Dave Allison2014-04-091-5/+25
| | | | | | | | | This reverts commit 081f73e888b3c246cf7635db37b7f1105cf1a2ff. Change-Id: Ibd777f8ce73cf8ed6c4cb81d50bf6437ac28cb61 Conflicts: compiler/dex/quick/mir_to_lir.h
* Revert "Use trampolines for calls to helpers"Dave Allison2014-04-071-25/+5
| | | | | | This reverts commit 754ddad084ccb610d0cf486f6131bdc69bae5bc6. Change-Id: Icd979adee1d8d781b40a5e75daf3719444cb72e8
* Use trampolines for calls to helpersDave Allison2014-04-041-5/+25
| | | | | | | | | | | | | | | | | | | | | | This is an ARM specific optimization to the compiler that uses trampoline islands to make calls to runtime helper functions. The intention is to reduce the size of the generated code (by 2 bytes per call) without affecting performance. By default this is on when generating an OAT file. It is off when compiling to memory. To switch this off in dex2oat, use the command line option: --no-helper-trampolines Enhances disassembler to print the trampoline entry on the BL instruction like this: 0xb6a850c0: f7ffff9e bl -196 (0xb6a85000) ; pTestSuspend Bug: 12607709 Change-Id: I9202bdb7cf21252ad807bd48701f1f6ce8e3d0fe
* Disassemble Thumb2 shifts and more VFP instructions.Vladimir Marko2014-04-031-117/+192
| | | | | | | | | | | | | Disassemble Thumb2 instructions LSL, LSR, ASR, ROR and VFP instructions VABS, VADD, VSUB, VMOV, VMUL, VNMUL, VDIV. Clean up disassembly of VCMP, VCMPE, VNEG and VSQRT. These could have been erroneously used for other insns (VSQRT for VMOV was encountered) and one VSQRT branch was unreachable. Remove duplicate VMOV opcodes from compiler. Change-Id: I160a1e3e4b6eabb6a5101ce348ffd49c0573257d
* Allow mixing of thread offsets between 32 and 64bit architectures.Ian Rogers2014-04-013-7/+11
| | | | | | | Begin a more full implementation x86-64 REX prefixes. Doesn't implement 64bit thread offset support for the JNI compiler. Change-Id: If9af2f08a1833c21ddb4b4077f9b03add1a05147
* Relaxed memory barriers for x86Razvan A Lupusoru2014-03-261-0/+6
| | | | | | | | | | X86 provides stronger memory guarantees and thus the memory barriers can be optimized. This patch ensures that all memory barriers for x86 are treated as scheduling barriers. And in cases where a barrier is needed (StoreLoad case), an mfence is used. Change-Id: I13d02bf3f152083ba9f358052aedb583b0d48640 Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
* Fix imm5 and shift_type detectionDmitriy Ivanov2014-03-251-3/+3
| | | | | Bug: 13628315 Change-Id: I8ff044cc18721b7ea50c75c796a2fb63a1e189f9
* x86-64 disassembler support.Ian Rogers2014-03-148-32/+43
| | | | Change-Id: I0ae39ae1ffdae2500ff368354f9e4702445176f0
* Avoid bus error from reading unaligned 64-bit literalBrian Carlstrom2014-03-131-1/+2
| | | | Change-Id: I5932f130e6a8d31e09ef615e8544ff0e1073ede9
* Merge "AArch64: Add ARM64 Disassembler"Ian Rogers2014-03-104-2/+101
|\
| * AArch64: Add ARM64 DisassemblerSerban Constantinescu2014-03-104-2/+101
| | | | | | | | | | | | | | This patch adds disassembler support for ARM64 based on VIXL. Change-Id: Ic7f5e197350809632145d932dbae8f6c16aebd13 Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
* | ARM: Remove duplicated instructions; add vcvt, vmla, vmls disassembler.Zheng Xu2014-03-101-0/+86
|/ | | | | | | Remove kThumb2VcvtID in the assembler which was duplicated. Add vcvt, vmla, vmls in the disassembler. Change-Id: I14cc39375c922c9917274d8dcfcb515e888fdf26
* Fix clang to compile and run host tests.Ian Rogers2014-02-281-4/+0
| | | | | | | | | | | | | | Don't use the computed goto interpreter with clang 3.4 as it causes compilation to hang. Avoid inclusion of LLVM_(HOST|DEVICE)_BUILD_MK except for with portable as it sets clang incompatible cflags. Most fixes are self-evident, for the quick dex file method inliner the enums were being used with ostreams, so fix the enums and operator out python script to allow this. Note this change effects portable but this is untestable as portable was broken by ELF file and mc linker changes. Change-Id: Ia54348f6b1bd3f76d3b71c6e8c5f97626386b903
* Inline x86 String.indexOfMark Mendell2014-02-201-0/+4
| | | | | | | | Take advantage of the presence of a constant search char or start index to tune the generated code. Change-Id: I0adcf184fb91b899a95aa4d8ef044a14deb51d88 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* art: convert makefiles to support multilib buildColin Cross2014-02-181-2/+0
| | | | | | | | Convert makefiles to allow for building two architectures at the same time. More changes may be necessary to get the tests to build. Change-Id: I02ba11706b7e5b5592d76e43c167bcbf0e665b93
* Support to generate inline long to FP bytecodes for x86Razvan A Lupusoru2014-02-111-0/+14
| | | | | | | | long-to-float and long-to-double are now generated inline instead of calling a helper routine. The conversion is done by using x87. Change-Id: I196e526afec1be212898baceca8527549c3655b6 Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
* Object model changes to support 64bit.Ian Rogers2014-02-061-1/+3
| | | | | | | | | | | | | | | | | | | | | | | Modify mirror objects so that references between them use an ObjectReference value type rather than an Object* so that functionality to compress larger references can be captured in the ObjectRefererence implementation. ObjectReferences are 32bit and all other aspects of object layout remain as they are currently. Expand fields in objects holding pointers so they can hold 64bit pointers. Its expected the size of these will come down by improving where we hold compiler meta-data. Stub out x86_64 architecture specific runtime implementation. Modify OutputStream so that reads and writes are of unsigned quantities. Make the use of portable or quick code more explicit. Templatize AtomicInteger to support more than just int32_t as a type. Add missing, and fix issues relating to, missing annotalysis information on the mutator lock. Refactor and share implementations for array copy between System and uses elsewhere in the runtime. Fix numerous 64bit build issues. Change-Id: I1a5694c251a42c9eff71084dfdd4b51fff716822
* Specializing x86 range argument copyingRazvan A Lupusoru2014-02-051-0/+36
| | | | | | | | | | The ARM implementation of range argument copying was specialized in some cases. For all other architectures, it would fall back to generating memcpy. This patch updates the x86 implementation so it does not call memcpy and instead generates loads and stores, favoring movement of 128-bit chunks. Change-Id: Ic891e5609a4b0e81a47c29cc5a9b301bd10a1933 Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
generated by cgit v1.1 at 2024-05-14 15:00:26 +0000