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* MIPS: Initial version of optimizing compiler for MIPS64R6.Roland Levillain2015-06-262-2/+143
| | | | | | | | | | (cherry picked from commit 4dda3376b71209fae07f5c3c8ac3eb4b54207aa8) (amended for mnc-dev) Bug: 21555893 Change-Id: I874dc356eee6ab061a32f8f3df5f8ac3a4ab7dcf Signed-off-by: Alexey Frunze <Alexey.Frunze@imgtec.com> Signed-off-by: Douglas Leung <douglas.leung@imgtec.com>
* Fix for incorrect encode and parse of PEXTRW instructionnikolay serdjuk2015-04-291-0/+8
| | | | | | | | | | | | The instruction PEXTRW encoded by sequence 66 0F 3A 15 was incorrectly encoded in compiler table and incorrectly parsed by disassembler. Signed-off-by: nikolay serdjuk <nikolay.y.serdjuk@intel.com> (cherry picked from commit e0705f51fdc71e9670a29f8c3a47168f50724b35) Change-Id: I7f051e23789aa3745d6eb854c97f80c475748b74
* Replace NULL with nullptrMathieu Chartier2015-04-221-1/+1
| | | | | | | Also fixed some lines that were too long, and a few other minor details. Change-Id: I6efba5fb6e03eb5d0a300fddb2a75bf8e2f175cb
* Merge "[MIPS] Refactoring code for disassembler"Andreas Gampe2015-04-096-348/+64
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| * [MIPS] Refactoring code for disassemblerGoran Jakovljevic2015-04-096-348/+64
| | | | | | | | | | | | Code for mips64 is merged with code for mips. Change-Id: I2e3f2118c69a189787ae8e7f09adb4ee5c0d00d9
* | Merge "Fix for incorrect parse of PEXTRW instruction"Andreas Gampe2015-04-091-1/+1
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| * Fix for incorrect parse of PEXTRW instructionnikolay serdjuk2015-04-071-1/+1
| | | | | | | | | | | | | | | | | | | | The instruction PEXTRW encoded by sequence 66 0F C5 has form: PEXTRW reg, xmm, imm8. Its reg is encoded in the REG part and xmm is encoded in the R/M part of ModR/M byte. Since the order is opposite to the PEXTRB and PEXTRD, we have to set 'load' to true and 'store' leave as false. Change-Id: I32c42ea005eec29f7bf969f275c36ffa0a95fa6d
* | Merge "Fix address formatting in Mips64 disassembler."David Srbecky2015-04-071-7/+4
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| * | Fix address formatting in Mips64 disassembler.David Srbecky2015-04-061-7/+4
| |/ | | | | | | | | | | | | Use FormatInstructionPointer like all the other disassemblers. This ensures that the 'absolute_addresses' option is honoured. Change-Id: I5580319cc4fad40e00f3fbbde25b142f7c689390
* | Merge "Build 32-bit version of the disassembler as well."David Srbecky2015-04-071-0/+2
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| * | Build 32-bit version of the disassembler as well.David Srbecky2015-04-061-0/+2
| |/ | | | | | | Change-Id: I22ecc2611c3b05b1031b42abdb5bf8c245220e03
* | ART: Enable more Clang warningsAndreas Gampe2015-04-062-2/+0
|/ | | | Change-Id: Ie6aba02f4223b1de02530e1515c63505f37e184c
* Merge "[optimizing] Implement x86/x86_64 math intrinsics"Andreas Gampe2015-04-021-0/+18
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| * [optimizing] Implement x86/x86_64 math intrinsicsMark Mendell2015-04-011-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement floor/ceil/round/RoundFloat on x86 and x86_64. Implement RoundDouble on x86_64. Add support for roundss and roundsd on both architectures. Support them in the disassembler as well. Add the instruction set features for x86, as the 'round' instruction is only supported if SSE4.1 is supported. Fix the tests to handle the addition of passing the instruction set features to x86 and x86_64. Add assembler tests for roundsd and roundss to x86_64 assembler tests. Change-Id: I9742d5930befb0bbc23f3d6c83ce0183ed9fe04f Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* | ARM64: Update to VIXL 1.9.Serban Constantinescu2015-03-311-2/+2
|/ | | | | | | Update VIXL's interface to VIXL 1.9. Change-Id: Iebae947539cbad65488b7195aaf01de284b71cbb Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
* ART: Add Mips32r6 backend supportDouglas Leung2015-03-201-4/+8
| | | | | | | | | Add Mips32r6 compiler support. Don't use deprecated Mips32r2 instructions if running in Mips32r6 mode. Change-Id: I54e689aa8c026ccb75c4af515aa2794f471c9f67
* Initial support for quick compiler on MIPS64r6.Maja Gagic2015-03-061-62/+66
| | | | Change-Id: I6f43027b84e4a98ea320cddb972d9cf39bf7c4f8
* ART: Enable the use of relative addresses in the arm64 disassembler.Alexandre Rames2015-03-062-24/+16
| | | | | | | | | Also, only keep register aliases for the link register 'lr' and the thread register 'tr' in the arm64 disassembler. Other aliases are not very important, and this way we don't have to provide aliases specialised for Quick or Optimizing. Change-Id: Ie7a04910f0c587710a0cf2648203d7e89eab5d1f
* ART: Fix Mips disassembler for some floating point instructions.Douglas Leung2015-02-281-21/+26
| | | | Change-Id: I2b661a8dae4cd924c081df85f570007cf645769c
* ARM/ARM64: Dump thread offset.Zheng Xu2015-02-032-26/+32
| | | | | | | | | | | | Dump thread offset in compiler verbose log for arm32/arm64 and oatdump for arm64. Before patch : 0x4e: ldr lr, [rSELF, #604] After patch : 0x4e: ldr lr, [rSELF, #604] ; pTestSuspend Change-Id: I514e69dc44b1cf4c8a8fa085b31f93cf6a1b7c91
* Merge "ART: Fix x86 disassembler"Andreas Gampe2015-02-021-10/+16
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| * ART: Fix x86 disassemblerAndreas Gampe2015-01-271-10/+16
| | | | | | | | | | | | | | | | Index 4 in SIB is valid when given Rex.x, where it denotes r12 and not the invalid rsp. Bug: 19149560 Change-Id: I1a74bcbb1ccf3686e45a3df5d852a86444f9d850
* | Add options for building/testing with coverage.Dan Albert2015-01-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | acov --clean mm -B NATIVE_COVERAGE=true ART_COVERAGE=true test-art-host acov --host -B is needed because you need to be sure you rebuild *all* of ART with coverage. Change-Id: Ib94ef610bd1b44dc45624877710ed733051b7a50
* | Remove libcxx.mk cruft.Dan Albert2015-01-291-1/+0
|/ | | | | | This is on by default now. No need to leave it in the makefiles. Change-Id: I20eab7426da4bbbf8b70ffc5b9af7b97487d885d
* ART: Allow to compile interpret-only mips64 filesAndreas Gampe2015-01-154-0/+334
| | | | | | | | | | | | Include enough infrastructure to allow cross-compiling for mips64, interpret-only. This includes the instruction-set-features, frame size info and utils assembler. Also add a disassembler for oatdump, and support in patchoat. Note: the runtime cannot run mips64, yet. Change-Id: Id106581fa76b478984741c62a8a03be0f370d992
* ART: Use jalr instead of jr for MipsAndreas Gampe2015-01-131-0/+2
| | | | | | Use the jalr instruction instead of jr in stubs and compiled code. Change-Id: Idacc5167a5bb0113dc2e7716e4767e5ed07b5e0b
* Improve Thumb disassembler for LDR/STR/PUSH/POP/BKPT.Vladimir Marko2015-01-061-232/+222
| | | | | | | | | | | | | Disassemble 16-bit Thumb PUSH, POP, BKPT. Clean up 32-bit load/store to handle all cases (including previously unrecognized indexed load/store) in one place; this also fixes LDRSH erroneously disassembled as LDRSB. Recognize more UNDEFINED instructions and other minor cleanup. Change-Id: Ifdd177745b70e3f774cc0469deb81191b035f51b
* Fix crash in x86 disassembler.Nicolas Geoffray2014-12-161-1/+1
| | | | | | Probably a typo from last refactoring. Change-Id: I086a87120ca0f0dfddbe803573b0e0f79cc6d945
* ART: Do not inline elf writer debug symbolsAndreas Gampe2014-12-151-2/+2
| | | | | | | | | Using Clang, this pushes the frame size of the caller across our limit. Thus forbid inlining. The function is only called once per compile, impact is insignificant. Bug: 18738594 Change-Id: I19c3f1168a5104ab508a8dbf9f2a8c035cb97e3c
* ART: Break up x86 disassembler main functionAndreas Gampe2014-12-152-237/+281
| | | | | | | | The function leads to large stack frames with Clang. Break out some parts and use four char* variables for opcode. Bug: 18733806 Change-Id: I8bf6da6c763175d7081c4231fa5d3b6809316220
* ARM: Combine multiply accumulate operations.Ningsheng Jian2014-12-111-1/+1
| | | | | | | Try to combine integer multiply and add(sub) into a MAC operation. For AArch64, also try to combine long type multiply and add(sub). Change-Id: Ic85812e941eb5a66abc355cab81a4dd16de1b66e
* Vixl: Update the VIXL interface to VIXL 1.7 and enable VIXL debug.Serban Constantinescu2014-11-282-2/+6
| | | | | | | | This patch updates the interface to VIXL 1.7 and enables the debug version of VIXL when ART is built in debug mode. Change-Id: I443fb941bec3cffefba7038f93bb972e6b7d8db5 Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
* Merge "Improvements to the ARM64 disassembler."Ian Rogers2014-11-193-5/+115
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| * Improvements to the ARM64 disassembler.Alexandre Rames2014-10-293-5/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This contains three changes: - Use register aliases in the disassembly. - When loading from a literal pool, show what is being loaded. - Disassemble using absolute addresses on ARM64. This ensures that addresses disassembled are coherent with instruction location addresses shown. Examples of disassembled instructions before and after the changes: Before: movz w17, #0x471f ldr d9, pc+736 (addr 0x72690d50) After: movz wip1, #0x471f ldr d9, pc+736 (addr 0x72690d50) (-745.133) Change-Id: I72fdc160fac26f74126921834f17a581c26fd5d8
* | Revert "Arm64: Use the debug version of VIXL for debug builds."Nicolas Geoffray2014-11-171-5/+1
| | | | | | | | | | | | This reverts commit 195c576fbff290d4c313b67ed24ca36f2531acc4. Change-Id: Id992a43ae346bb4c38a6c47639b02aea838d974a
* | Arm64: Use the debug version of VIXL for debug builds.Serban Constantinescu2014-11-141-1/+5
| | | | | | | | | | | | | | | | This patch builds the debug version of ART against VIXL debug. In this way VIXL will assert misuses of the assembler and disassembler. Change-Id: Ic4654eb20e420f23b40e96a69be452dc50770c1c Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
* | Instruction set features for ARM64, MIPS and X86.Ian Rogers2014-11-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Also, refactor how feature strings are handled so they are additive or subtractive. Make MIPS have features for FPU 32-bit and MIPS v2. Use in the quick compiler rather than #ifdefs that wouldn't have worked in cross-compilation. Add SIMD features for x86/x86-64 proposed in: https://android-review.googlesource.com/#/c/112370/ Bug: 18056890 Change-Id: Ic88ff84a714926bd277beb74a430c5c7d5ed7666
* | Tidy x86 disassemblerIan Rogers2014-11-071-24/+84
| | | | | | | | Change-Id: I2f0a2851a15f5a099a5bc0249e3ea0616cdcd94e
* | ART: More warningsAndreas Gampe2014-11-042-44/+8
| | | | | | | | | | | | | | Enable -Wno-conversion-null, -Wredundant-decls and -Wshadow in general, and -Wunused-but-set-parameter for GCC builds. Change-Id: I81bbdd762213444673c65d85edae594a523836e5
* | Tidy and reduce ART library dependencies on the host.Ian Rogers2014-10-301-2/+2
|/ | | | | | | Move to shared rather than static libraries. Avoids capture of all static libraries library dependencies. Change-Id: I2be96e92dad4ed1842d76b044745f2a2e15372eb
* Tidy logging code not using UNIMPLEMENTED.Ian Rogers2014-10-241-2/+2
| | | | Change-Id: I7a79c1671a6ff8b2040887133b3e0925ef9a3cfe
* C++11 related clean-up of DISALLOW_..Ian Rogers2014-10-225-6/+7
| | | | | | | | | | | | | | | | | | Move DISALLOW_COPY_AND_ASSIGN to delete functions. By no having declarations with no definitions this prompts better warning messages so deal with these by correcting the code. Add a DISALLOW_ALLOCATION and use for ValueObject and mirror::Object. Make X86 assembly operand types ValueObjects to fix compilation errors. Tidy the use of iostream and ostream. Avoid making cutils a dependency via mutex-inl.h for tests that link against libart. Push tracing dependencies into appropriate files and mutex.cc. x86 32-bit host symbols size is increased for libarttest, avoid copying this in run-test 115 by using symlinks and remove this test's higher than normal ulimit. Fix the RunningOnValgrind test in RosAllocSpace to not use GetHeap as it returns NULL when the heap is under construction by Runtime. Change-Id: Ia246f7ac0c11f73072b30d70566a196e9b78472b
* Tidy up logging.Ian Rogers2014-10-223-0/+3
| | | | | | | | | | | | | | | | | Move gVerboseMethods to CompilerOptions. Now "--verbose-methods=" option to dex2oat rather than runtime argument "-verbose-methods:". Move ToStr and Dumpable out of logging.h, move LogMessageData into logging.cc except for a forward declaration. Remove ConstDumpable as Dump methods are all const (and make this so if not currently true). Make LogSeverity an enum and improve compile time assertions and type checking. Remove log_severity.h that's only used in logging.h. With system headers gone from logging.h, go add to .cc files missing system header includes. Also, make operator new in ValueObject private for compile time instantiation checking. Change-Id: I3228f614500ccc9b14b49c72b9821c8b0db3d641
* Make ART compile with GCC -O0 again.Ian Rogers2014-10-161-0/+1
| | | | | | | | | | | | | Tidy up InstructionSetFeatures so that it has a type hierarchy dependent on architecture. Add to instruction_set_test to warn when InstructionSetFeatures don't agree with ones from system properties, AT_HWCAP and /proc/cpuinfo. Clean-up class linker entry point logic to not return entry points but to test whether the passed code is the particular entrypoint. This works around image trampolines that replicate entrypoints. Bug: 17993736 Change-Id: I5f4b49e88c3b02a79f9bee04f83395146ed7be23
* ART: ARM64: Fix instruction addresses in the disassembly.Alexandre Rames2014-10-131-7/+3
| | | | Change-Id: Ic8b6e0d5cd15e029de9bc82e0a4fc2e33d07936c
* Enable -Wimplicit-fallthrough.Ian Rogers2014-10-092-6/+7
| | | | | | | | Falling through switch cases on a clang build must now annotate the fallthrough with the FALLTHROUGH_INTENDED macro. Bug: 17731372 Change-Id: I836451cd5f96b01d1ababdbf9eef677fe8fa8324
* ART: Fix some -Wpedantic errorsAndreas Gampe2014-09-292-14/+14
| | | | | | | | | | | | | | | | Remove extra semicolons. Dollar signs in C++ identifiers are an extension. Named variadic macros are an extension. Binary literals are a C++14 feature. Enum re-declarations are not allowed. Overflow. Change-Id: I7d16b2217b2ef2959ca69de84eaecc754517714a
* Avoid printing absolute addresses in oatdumpBrian Carlstrom2014-09-1610-32/+75
| | | | | | | | | | | | | | | | | - Added printing of OatClass offsets. - Added printing of OatMethod offsets. - Added bounds checks for code size size, code size, mapping table, gc map, vmap table. - Added sanity check of 100k for code size. - Added partial disassembly of questionable code. - Added --no-disassemble to disable disassembly. - Added --no-dump:vmap to disable vmap dumping. - Reordered OatMethod info to be in file order. Bug: 15567083 (cherry picked from commit 34fa79ece5b3a1940d412cd94dbdcc4225aae72f) Change-Id: I2c368f3b81af53b735149a866f3e491c9ac33fb8
* ART: Vectorization opcode implementation fixesLupusoru, Razvan A2014-09-031-59/+34
| | | | | | | | | This patch fixes the implementation of the x86 vectorization opcodes. Change-Id: I0028d54a9fa6edce791b7e3a053002d076798748 Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com> Signed-off-by: Udayan Banerji <udayan.banerji@intel.com> Signed-off-by: Philbert Lin <philbert.lin@intel.com>
* ART: Add non-temporal store supportJean Christophe Beyler2014-08-261-0/+1
| | | | | | | | | | | Added non-temporal store support as a hint from the ME. Added the implementation of the memory barrier extended instruction that supports non-temporal stores by explicitly serializing all previous store-to-memory instructions. Change-Id: I8205a92083f9725253d8ce893671a133a0b6849d Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com> Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
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