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* Quick compiler: fix x86 special identitybuzbee2014-11-192-0/+27
| | | | | | | | | | | | The Quick compiler recognizes and specially handles a set of small methods - including those that simply return one of their arguments. For x86, special identity was broken if the returned argument was a double that was passed half in register and half in memory. internal b/17325447 Change-Id: I3a766977cdc0b4216d8ad65a9870c3250b32471e
* am c39eb4ae: Merge "Add regression test for null check elimination."Vladimir Marko2014-10-132-0/+20
|\ | | | | | | | | * commit 'c39eb4aef19b7fe64283fb3ae7ce6d13cd6c8294': Add regression test for null check elimination.
| * Add regression test for null check elimination.Vladimir Marko2014-10-132-0/+20
| | | | | | | | | | | | | | | | Prompted by https://android-review.googlesource.com/110090 Bug: 17969907 Change-Id: I938c27cda0681b9431d69baf4eafa7ca2f9b5c9c
| * Quick compiler (arm64) Fix inline Math.round()buzbee2014-09-122-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | Math.round is detected and inlined for arm64. However, the arm64 backend incorrectly modified a source operand in place during the round sequence. Depending on how registers are allocated, that modification could persist. Changed to use a temp register for the intermediate result. Internal b/17411468 Change-Id: I7c636f985e193f8ff838768fde3b741e443bb1bb
* | Quick compiler: aarch64 codegen & long_min literalbuzbee2014-09-262-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | Int64 overflow during instruction selection caused incorrect code patterns to emitted in some cases of long operations with an immediate value of 0x8000000000000000. The code in question was attempting to determine if the immediate operand would fit in aarch64 immediate instruction variants. Internal b/17630605 Change-Id: I8177021b73e51302bc1032387d83b1dd567ed6db
* | Quick compiler (arm64) Fix inline Math.round()buzbee2014-09-122-0/+13
|/ | | | | | | | | | | | Math.round is detected and inlined for arm64. However, the arm64 backend incorrectly modified a source operand in place during the round sequence. Depending on how registers are allocated, that modification could persist. Changed to use a temp register for the intermediate result. Internal b/17411468 Change-Id: I7c636f985e193f8ff838768fde3b741e443bb1bb
* ART: LoadConstWide should clobber temp regAlexei Zavjalov2014-07-312-0/+16
| | | | | | | | | | If we have 2+ LoadConstWide(FP) calls in one method it is possible that LoadConstWide will load the method poiner only once. In some cases, for example, if we have branches, initialization might not be done and it may lead to a segmentation fault. Change-Id: If45fc2d1109d7ce9bd272f5c56446b2a6884daac Signed-off-by: Alexei Zavjalov <alexei.zavjalov@intel.com>
* Fix null pointer check elimination for catch entries.Vladimir Marko2014-07-222-0/+24
| | | | | | | | | | | Remove the special treatment of catch blocks for null pointer check elimination and class initialization check elimination. In both cases this can help optimizing previously missed cases. In the null check case, this avoids incorrect optimization as exposed by the new test. Bug: 16230771 Change-Id: I834b7a1835d9ca8572f4f8d8516d93913c701ad1
* ART: Add another special case to GenSelect for ARM64Andreas Gampe2014-07-121-0/+3
| | | | | | | This adds a special case for a select of two constants that have a difference of exactly one. Change-Id: I6e8bea791cb25af1b855d62e2333fd7fe6ac4e3a
* Handle potential <clinit>() correctly in LVN.Vladimir Marko2014-07-092-0/+31
| | | | | Bug: 16177324 Change-Id: I727ab6ce9aa9a608fe570cf391a6b732a12a8655
* Skip BBs without SSA representation in the Constant Propagation phaseAlexei Zavjalov2014-04-212-0/+28
| | | | | | | | | | In some cases the constant propagation optimization may get the MIR graph where some of the BBs have no predecessors and do not transformed to the SSA form. If such BB has operations on constants this may lead to segfault. This patch adds the condition that will pass the only BBs with SSA. Change-Id: I816d46b2492c5bd4748f983c3725b4798f9ebd68 Signed-off-by: Alexei Zavjalov <alexei.zavjalov@intel.com>
* Inlining setters that return one of their arguments.Vladimir Marko2014-04-072-0/+744
| | | | | | | | Useful for builder classes and synthetic setters. The latter are not inlined yet since they are static methods, i.e. they don't use "this" as the object for IPUT. Change-Id: I3d34156c3629b837a0a95ccc34a8aae3f4a636d5
* Error when taking the modulo of the length of an arrayBrian Carlstrom2014-03-272-0/+27
| | | | | Bug: 13679511 Change-Id: I4c694a9d85727af8095091c42f1ac00a78ba4ea2
* Fix CopyRegInfo to keep live/dirty flags of new registers.Chao-ying Fu2014-03-272-0/+34
| | | | | | | | | CopyRegInfo should not change live/dirty flags of new registgers. Otherwise, it will lead to incorrectly clobbering these live registers that are not live actually, and then allocating them to another usage. Change-Id: Ia9f055b33a11a6d70c0aca1a9fe8639ecfb09464 Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
* Reuse promoted register temporarilyYevgeny Rouban2014-03-262-0/+14
| | | | | | | | | | | | | | | | | AtomicLong (x86) is implemented as an intrinsic, which uses the cmpxchng8b instruction. This instruction requires 4 physical registers plus 2 more used for the memory operand. On x86 we have only 4 temporaries. The code tried to solve this by using MarkTemp utility, but this was not meant to be used with promoted registers. The problem is that MarkTemp does not spill anything and as a result we can lose VR. If the registers are promoted this patch just reuses the values pushed on the stack. Change-Id: Ifec9183e2483cf704d0d1166a1004a9aa07b4f1d Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com> Signed-off-by: Yevgeny Rouban <yevgeny.y.rouban@intel.com>
* Fix message in 083-compiler_regressions testbuzbee2014-03-201-1/+1
| | | | | | Fix test failure message to reflect expected result. Change-Id: I75ae3e882671aa429ecb17487188720c19ff4d32
* Fix Quick compiler "out of registers"buzbee2014-03-192-0/+299
| | | | | | | | | | | | | | | | | | | There are a few places in the Arm backend that expect to be able to survive on a single temp register - in particular entry code generation and argument passing. However, in the case of a very large frame and floating point ld/st, the existing code could end up using 2 temps. In short, if there is a displacement overflow we try to use indexed load/store instructions (slightly more efficient). However, there are none for floating point - so we ended up burning yet another register to construct a direct pointer. This CL detects this case and doesn't try to use the indexed load/store mechanism for floats. Fix for https://code.google.com/p/android/issues/detail?id=67349 Change-Id: I1ea596ea660e4add89fd4fddb8cbf99a54fbd343
* Rewrite kMirOpSelect for all IF_ccZ opcodes.Vladimir Marko2014-03-042-0/+113
| | | | | | Also improve special cases for ARM and add tests. Change-Id: I06f575b9c7b547dbc431dbfadf2b927151fe16b9
* Incorrect result of the "mul-long by 1" operationAlexei Zavjalov2014-02-262-0/+15
| | | | | | | | | | | | ART handles "mul-long by 1" as a special case and try to alloc a new pair of regs through the EvalLocWide method and then put there the multiplicand through the StoreValueWide method. But in case when both multiplicand and multiplier are constants, it will not place correct values in a new reg pair and result of calculations will be incorrect. The new solution uses the only StoreValueWide method. Change-Id: I3d6947737c92c5a12f2840003b17a427e31d288f Signed-off-by: Alexei Zavjalov <alexei.zavjalov@intel.com>
* Add tests for null check elimination by local value numbering.Vladimir Marko2014-02-212-1/+51
| | | | Change-Id: I0c3355b3c38b8830fffe2233ede7f6a35488b6fe
* Add wide setter test with preceding parameters as int.Vladimir Marko2014-02-101-2/+27
| | | | Change-Id: Ieeef0318d140aad963f75e5d14938e5e7a9eec41
* Tweak test to better expose codegen bug.Ian Rogers2014-02-071-4/+4
| | | | | | Place a non-zero value in high 32bits. Change-Id: I6ff42de39d56c4e4d6f44eb0001460ba6d58aa75
* Update ART tests to handle new System.gc behaviorMathieu Chartier2014-02-041-2/+2
| | | | | | | | | | Changed calls from System.gc to Runtime.getRuntime.gc where it was necessary. Required for: https://android-review.googlesource.com/#/c/80253/ Change-Id: I2b0622585da54229a6248e95d40134b6d18598a9
* Bring over the new tests from ↵Elliott Hughes2012-07-113-0/+53
| | | | | | | | | https://android-review.googlesource.com/#/c/38771/. (The bug itself had already been fixed in art's compiler, because we always run compiled code. I've also removed the JIT warmup code.) Change-Id: I9d1d2b68f99dd06887146fdd05cb2e4537b4d5fc
* Fix getter/setter special case codegenbuzbee2012-03-271-2/+14
| | | | | | | | | | | | | | | The special-purpose code generators for simple methods that get or set and instance field and then return require that no throws are possible. The previous code incorrectly relied on the first argument being a "this" pointer, and thus previously null-checked. This did not take into account the possibility of a static method which happened to pass an object referece as it's first argument. The fix is to avoid making any assumptions, but rather rely solely on the results of the null-check elimination pass which will correctly recoginize the "this" case. Change-Id: Icf001a10a19234cf3f4d87cf1baede93fdf0360c
* Fix cpplint's whitespace complaints.Elliott Hughes2012-03-261-2/+2
| | | | Change-Id: I11fd2db2badf7bd98e7866ca2155d8ef1e112408
* Fix special method codegenbuzbee2012-03-213-0/+8429
Tightened up the conditions under which we can generate frameless methods. Added and renamed test case. Added special handling for identity functions. Change-Id: I5b04ea222becefc151ef7ff6b255e58922ccd6f2
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