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* ART: Fix divide-by-zero for ARMAndreas Gampe2015-01-061-0/+1
| | | | | | | | There was an infinite loop in the code generation for a divide by literal zero. Bug: 18887754 Change-Id: Ibd481918d3c6d7bc62fdd1a6807042009f561d95
* ART: Fix verification of constructors.Stephen Kyle2014-12-221-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: A constructor must call its superclass constructor. However, if one replaces the invoke-direct superclass.<init>() instruction with a variety of instructions, the verifier would NOT complain that the superclass constructor hadn't been called. Detailed explanation: This was because if we are verifying the return-void insn of a constructor, then we check that the register line doesn't contain a register with an UninitializedThis type. With a method like follows: Class.<init>()V: return-void Then we hit the return-void, see the UninitializedThis, and fail the method. However, with a method like follows: Class.<init>()V: nop return-void Any insn that continues or branches onto a return-void instruction will mark all of the registers as Conflict. This meant that the check in return-void for an UninitializedThis residing the register line would _always_ pass if there were any insns before it - the entire line had been set to Conflict. The fix is to bring the check for an UninitializedThis forward to the point just before we set all registers to Conflict, if we're about to hit a return-void insn in a constructor. It still needs to be done again in the verification of return-void itself, to avoid the solo return-void case. This patch also deals with the case where the only remaining UninitializedThis reference is overwritten, to avoid a method like the following from getting through verification: Class.<init>()V: const/4 v0, 0 return-void Bug: 18800943 Change-Id: I2e317261844d3b6c78e35228669f3da173316570 Fuzzed-With: https://android-review.googlesource.com/#/c/119463/
* Clean up dead loops before suspend check elimination.Vladimir Marko2014-12-191-0/+1
| | | | | | | | Get rid of BasicBlock::KillUnreachable() and just Kill() unreachable blocks from the DFS order calculation. Bug: 18718277 Change-Id: Icaf7b9c2320530e950f87e1e2e2bd1fa5f53cb98
* Re-factor Quick ABI supportSerguei Katkov2014-12-081-0/+1
| | | | | | | | | | | | | | | | | | | Now every architecture must provide a mapper between VRs parameters and physical registers. Additionally as a helper function architecture can provide a bulk copy helper for GenDalvikArgs utility. All other things becomes a common code stuff: GetArgMappingToPhysicalReg, GenDalvikArgsNoRange, GenDalvikArgsRange, FlushIns. Mapper now uses shorty representation of input parameters. This is required due to location are not enough to detect the type of parameter (fp or core). For the details see https://android-review.googlesource.com/#/c/113936/. Change-Id: Ie762b921e0acaa936518ee6b63c9a9d25f83e434 Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
* Fix Move64 by using ParallelMoves.Nicolas Geoffray2014-11-271-0/+1
| | | | | | | Destination and source might overlap in a Move64, so we have to use a parallel move resolver. Change-Id: Ica6c72d91ab8e2e2ee4661b211ac1ee8f054b9ef
* Quick compiler: handle embedded switch databuzbee2014-11-251-0/+2
| | | | | | | | | | | | Although switch data is generally placed at the end of a dex file by dx, it can occur elsewhere (and does via obsfucators). This CL fixes a parsing error related to embedded switch data by ensuring valid dex instructions following the embedded data appear in their own basic blocks. AOSP b/80600 Change-Id: I91ead6b398386bcf168b1088c5bc13a53b18f26e
* ART: X86Mir2Lir::OpRegRegReg should expect kOpMul for r_dest == r_src2 casePavel Vyssotski2014-11-191-0/+1
| | | | | | | | | | | OpRegRegReg in case of r_dest == r_src2 does not expect kOpMul as valid operation. This provokes abort compiling instruction like "mul-int v0, v1, v0" if both operands are arriving in registers. The fix is to expect kOpMul as comutative operation. Change-Id: I259e49edea4b8b08ca4ed1c61033bbc2b2229078 Signed-off-by: Pavel Vyssotski <pavel.n.vyssotski@intel.com>
* Do not try to sharpen super calls to abstract methods.Vladimir Marko2014-11-181-0/+8
| | | | | | | | Bug: 18380491 (cherry picked from commit 474123dccc5aa9a0dfe566d332174877fd5b7040) Change-Id: I6637aaa562115f6b07d8637f0cc6658f1a6739bb
* Fix ordering of fields with the same name.Vladimir Marko2014-11-171-0/+1
| | | | | | | | | | | | While the Java language doesn't allow multiple fields with the same name in a single class (excluding fields from super classes), the bytecode specification permits it and tools such as proguard actually generate them. Define the order of these fields by their dex file index and relax the check of field ordering to permit identical names. Bug: 18211592 Change-Id: I1dee9b2b669a6ea180a2d3a41030efb2aed53950
* Avoid abort in malformed dex code.Ian Rogers2014-11-141-33/+47
| | | | | | | | | | Don't allow a perceived double monitor-enter on a register to abort libartd. Allow expected verifier errors in the smali tests. Tidy includes in the method verifier. Bug: 17978759 Change-Id: Ic44924c788cd2334f91a047fb41b459b89a1843b
* ART: GenNegLong incorrectly handled register overlap for x86nikolay serdjuk2014-11-101-0/+1
| | | | | | | | | | | | There is a bug in the GenNegLong: it should invoke OpRegCopy(temp_reg, rl_result.reg.GetHigh()); instead of OpRegCopy(temp_reg, rl_result.reg); But, anyway there is no need to handle the overlap anymore because it is already handled in OpRegCopyWide() which is invoked from StoreValueWide(). Change-Id: I379ed23434c72a91e875e753708387be6502bc57 Signed-off-by: nikolay serdjuk <nikolay.y.serdjuk@intel.com>
* ART: Prevent float inference back to SSA in-regs.Stephen Kyle2014-10-241-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | .method public static getInt(I)I .registers 2 const/4 v0, 0x0 if-ne v0, v0, :after float-to-int v0, v0 :exit add-int/2addr v0, v1 return v0 :after move v1, v0 goto :exit .end method In this code sample, v1 is the single parameter to this method. In one of the phi-nodes inserted between :exit and add-int/2addr, v1's two incoming SSA regs are: - the initial def of v1 as a parameter - the v1 def'd at move v1, v0. During type inference, because the 2nd def is a float (because of the earlier float-to-int v0, v0) this will change the type of the 1st def to a float as well, which is incorrect since the first parameter is known to be non-float. This fix checks during phi-node type-inference if an SSA reg that is the initial def of a parameter vreg is about to be set as float when it was not previously, and skips the inference if so. In this case, when using a hard-float ABI, having the in-reg v1 set as float causes FlushIns() to read the argument to the method from an FP reg, when the argument will be passed in a core reg by any caller. Also included is a smali test for this bug: compare difference between ./run-test --64 800 ./run-test --64 --interpreter 800 when the vreg_analysis patch has not been applied. (Requires 64-bit because 32-bit ARM currently does not use hard-float.) getInt(I)I should return its argument, but it returns an incorrect value. Change-Id: I1d4b5be6a931fe853279e89dd820820f29823da1 Signed-off-by: Stephen Kyle <stephen.kyle@arm.com>
* Use the shared smali test infrastructure for 800-smali.Nicolas Geoffray2014-10-231-17/+0
| | | | | | No need for a special build file now. Change-Id: I7f6813553548b48fb5f54640506d1a361d9db3c1
* ART: Add smali-based run-testAndreas Gampe2014-10-102-0/+139
Add run-test 800 for smali-based tests. To use, drop a smali file into the src/ directory and add a TestCase in src/Main.java. Bug: 17814475 Change-Id: Ica9eb830689862cb3a4ffa0019fbc447c01af744
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