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| author | QuIC Gerrit Code Review <gerrit@quicinc.com> | 2009-12-14 00:01:46 -0800 |
|---|---|---|
| committer | QuIC Gerrit Code Review <gerrit@quicinc.com> | 2009-12-14 00:01:46 -0800 |
| commit | 4ebbea8c6da01a220303388ab4c68c13a5ffbfc1 (patch) | |
| tree | 6dd41f74b1e31fd44f6e9611ce3d0c89f18e861b | |
| parent | dfc37ee5aa586d4cb96d6638506c9be0263aab3b (diff) | |
| parent | aa9d1bebc8c5c6f782603f3958a8b26a4fd1509c (diff) | |
| download | bionic-4ebbea8c6da01a220303388ab4c68c13a5ffbfc1.zip bionic-4ebbea8c6da01a220303388ab4c68c13a5ffbfc1.tar.gz bionic-4ebbea8c6da01a220303388ab4c68c13a5ffbfc1.tar.bz2 | |
Merge change Iaa9d1beb into eclair
* changes:
bionic: remove V5 instruction for V6 targets
| -rw-r--r-- | libc/arch-arm/bionic/memcpy.S | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/libc/arch-arm/bionic/memcpy.S b/libc/arch-arm/bionic/memcpy.S index 024d885..ef4b399 100644 --- a/libc/arch-arm/bionic/memcpy.S +++ b/libc/arch-arm/bionic/memcpy.S @@ -260,20 +260,31 @@ cached_aligned32: * */ +#if __ARM_ARCH__ == 5 // Align the preload register to a cache-line because the cpu does // "critical word first" (the first word requested is loaded first). bic r12, r1, #0x1F add r12, r12, #64 +#endif 1: ldmia r1!, { r4-r11 } + +#if __ARM_ARCH__ == 5 PLD (r12, #64) +#else + PLD (r1, #64) +#endif + subs r2, r2, #32 +#if __ARM_ARCH__ == 5 // NOTE: if r12 is more than 64 ahead of r1, the following ldrhi // for ARM9 preload will not be safely guarded by the preceding subs. // When it is safely guarded the only possibility to have SIGSEGV here // is because the caller overstates the length. ldrhi r3, [r12], #32 /* cheap ARM9 preload */ +#endif + stmia r0!, { r4-r11 } bhs 1b |