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| author | Brian Steuer <bsteuer@quicinc.com> | 2009-12-11 12:36:25 -0800 |
|---|---|---|
| committer | Dinesh Garg <dgarg@codeaurora.org> | 2010-06-29 11:21:03 -0700 |
| commit | 738be4605e32d99c19b12f966fd76317c17b7d43 (patch) | |
| tree | 56cc5e2cca0ea1eda55213da3d8b78253a1a8c0b | |
| parent | 46d5ba55afd3884f9fd9febc9da021632828e4d1 (diff) | |
| download | bionic-738be4605e32d99c19b12f966fd76317c17b7d43.zip bionic-738be4605e32d99c19b12f966fd76317c17b7d43.tar.gz bionic-738be4605e32d99c19b12f966fd76317c17b7d43.tar.bz2 | |
bionic: remove V5 instruction for V6 targets
Instructions in memcpy that are only needed for ARMV5 targets
are now conditionally compiled for those targets.
| -rw-r--r-- | libc/arch-arm/bionic/memcpy.S | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/libc/arch-arm/bionic/memcpy.S b/libc/arch-arm/bionic/memcpy.S index 12e97c6..b8d1007 100644 --- a/libc/arch-arm/bionic/memcpy.S +++ b/libc/arch-arm/bionic/memcpy.S @@ -260,20 +260,31 @@ cached_aligned32: * */ +#if __ARM_ARCH__ == 5 // Align the preload register to a cache-line because the cpu does // "critical word first" (the first word requested is loaded first). bic r12, r1, #0x1F add r12, r12, #64 +#endif 1: ldmia r1!, { r4-r11 } + +#if __ARM_ARCH__ == 5 PLD (r12, #64) +#else + PLD (r1, #64) +#endif + subs r2, r2, #32 +#if __ARM_ARCH__ == 5 // NOTE: if r12 is more than 64 ahead of r1, the following ldrhi // for ARM9 preload will not be safely guarded by the preceding subs. // When it is safely guarded the only possibility to have SIGSEGV here // is because the caller overstates the length. ldrhi r3, [r12], #32 /* cheap ARM9 preload */ +#endif + stmia r0!, { r4-r11 } bhs 1b |