summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorLinux Build Service Account <lnxbuild@localhost>2011-01-14 00:23:14 -0800
committerQuIC Gerrit Code Review <code-review@localhost>2011-01-14 00:23:14 -0800
commite8ecfc3662d1396380d94524a686d0459e5bc92a (patch)
tree64281f8a11150ed81df971a32eb3c9ed48bd0345
parent19c624245624f3970dfe881d9c1df958cc76b53c (diff)
parentff45fe786f94c3528255672f8a69a8c2d8811bfb (diff)
downloadbionic-e8ecfc3662d1396380d94524a686d0459e5bc92a.zip
bionic-e8ecfc3662d1396380d94524a686d0459e5bc92a.tar.gz
bionic-e8ecfc3662d1396380d94524a686d0459e5bc92a.tar.bz2
Merge "bionic: remove V5 instruction for V6 targets" into gingerbread
-rw-r--r--libc/arch-arm/bionic/memcpy.S11
1 files changed, 11 insertions, 0 deletions
diff --git a/libc/arch-arm/bionic/memcpy.S b/libc/arch-arm/bionic/memcpy.S
index ba55996..ace7cc5 100644
--- a/libc/arch-arm/bionic/memcpy.S
+++ b/libc/arch-arm/bionic/memcpy.S
@@ -260,20 +260,31 @@ cached_aligned32:
*
*/
+#if __ARM_ARCH__ == 5
// Align the preload register to a cache-line because the cpu does
// "critical word first" (the first word requested is loaded first).
bic r12, r1, #0x1F
add r12, r12, #64
+#endif
1: ldmia r1!, { r4-r11 }
+
+#if __ARM_ARCH__ == 5
PLD (r12, #64)
+#else
+ PLD (r1, #64)
+#endif
+
subs r2, r2, #32
+#if __ARM_ARCH__ == 5
// NOTE: if r12 is more than 64 ahead of r1, the following ldrhi
// for ARM9 preload will not be safely guarded by the preceding subs.
// When it is safely guarded the only possibility to have SIGSEGV here
// is because the caller overstates the length.
ldrhi r3, [r12], #32 /* cheap ARM9 preload */
+#endif
+
stmia r0!, { r4-r11 }
bhs 1b