diff options
author | David 'Digit' Turner <digit@google.com> | 2010-06-10 23:34:24 -0700 |
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committer | David 'Digit' Turner <digit@google.com> | 2010-06-11 13:49:09 -0700 |
commit | 6c8a2f2a5bc8d612ee953f528f2b5eb35983656a (patch) | |
tree | 7dd45d3e3162220578e93a6cb7244b4209b1c7c5 | |
parent | 038fbae518e904c7aba64779714a22dbeeb90887 (diff) | |
download | bionic-6c8a2f2a5bc8d612ee953f528f2b5eb35983656a.zip bionic-6c8a2f2a5bc8d612ee953f528f2b5eb35983656a.tar.gz bionic-6c8a2f2a5bc8d612ee953f528f2b5eb35983656a.tar.bz2 |
libc: remove cutils dependencies
We simply copy the stuff we need from cutils headers.
A future patch will change cutils to include the private <bionic_atomic_inline.h>
Change-Id: Ib6fd9a03bc9e337ce867bd606dc94c2b4438480a
-rw-r--r-- | libc/bionic/logd_write.c | 9 | ||||
-rw-r--r-- | libc/bionic/pthread.c | 2 | ||||
-rw-r--r-- | libc/bionic/semaphore.c | 2 | ||||
-rw-r--r-- | libc/private/bionic_atomic_inline.h | 107 |
4 files changed, 116 insertions, 4 deletions
diff --git a/libc/bionic/logd_write.c b/libc/bionic/logd_write.c index 618160f..63dfd59 100644 --- a/libc/bionic/logd_write.c +++ b/libc/bionic/logd_write.c @@ -38,12 +38,17 @@ #include <stdarg.h> #include <fcntl.h> -#include <cutils/logger.h> #include "logd.h" +/* should match system/core/include/cutils/logger.h */ +#define LOGGER_LOG_MAIN "log/main" +#define LOGGER_LOG_RADIO "log/radio" +#define LOGGER_LOG_EVENTS "log/events" +#define LOGGER_LOG_SYSTEM "log/system" + #include <pthread.h> -#define LOG_BUF_SIZE 1024 +#define LOG_BUF_SIZE 1024 typedef enum { LOG_ID_NONE = 0, diff --git a/libc/bionic/pthread.c b/libc/bionic/pthread.c index ac5e6bf..8eee136 100644 --- a/libc/bionic/pthread.c +++ b/libc/bionic/pthread.c @@ -44,7 +44,7 @@ #include <assert.h> #include <malloc.h> #include <bionic_futex.h> -#include <cutils/atomic-inline.h> +#include <bionic_atomic_inline.h> #include <sys/prctl.h> #include <sys/stat.h> #include <fcntl.h> diff --git a/libc/bionic/semaphore.c b/libc/bionic/semaphore.c index 39d049a..0a6cab4 100644 --- a/libc/bionic/semaphore.c +++ b/libc/bionic/semaphore.c @@ -30,7 +30,7 @@ #include <sys/time.h> #include <sys/atomics.h> #include <time.h> -#include <cutils/atomic-inline.h> +#include <bionic_atomic_inline.h> #include <bionic_futex.h> /* Use the lower 31-bits for the counter, and the high bit for diff --git a/libc/private/bionic_atomic_inline.h b/libc/private/bionic_atomic_inline.h new file mode 100644 index 0000000..95766e1 --- /dev/null +++ b/libc/private/bionic_atomic_inline.h @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2010 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef BIONIC_ATOMIC_INLINE_H +#define BIONIC_ATOMIC_INLINE_H + +/* + * Inline declarations and macros for some special-purpose atomic + * operations. These are intended for rare circumstances where a + * memory barrier needs to be issued inline rather than as a function + * call. + * + * Most code should not use these. + * + * Anything that does include this file must set ANDROID_SMP to either + * 0 or 1, indicating compilation for UP or SMP, respectively. + * + * Macros defined in this header: + * + * void ANDROID_MEMBAR_FULL(void) + * Full memory barrier. Provides a compiler reordering barrier, and + * on SMP systems emits an appropriate instruction. + */ + +#if !defined(ANDROID_SMP) +# error "Must define ANDROID_SMP before including atomic-inline.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Define the full memory barrier for an SMP system. This is + * platform-specific. + */ + +#ifdef __arm__ +#include <machine/cpu-features.h> + +/* + * For ARMv6K we need to issue a specific MCR instead of the DMB, since + * that wasn't added until v7. For anything older, SMP isn't relevant. + * Since we don't have an ARMv6K to test with, we're not going to deal + * with that now. + * + * The DMB instruction is found in the ARM and Thumb2 instruction sets. + * This will fail on plain 16-bit Thumb. + */ +#if defined(__ARM_HAVE_DMB) +# define _ANDROID_MEMBAR_FULL_SMP() \ + do { __asm__ __volatile__ ("dmb" ::: "memory"); } while (0) +#else +# define _ANDROID_MEMBAR_FULL_SMP() ARM_SMP_defined_but_no_DMB() +#endif + +#elif defined(__i386__) || defined(__x86_64__) +/* + * For recent x86, we can use the SSE2 mfence instruction. + */ +# define _ANDROID_MEMBAR_FULL_SMP() \ + do { __asm__ __volatile__ ("mfence" ::: "memory"); } while (0) + +#else +/* + * Implementation not defined for this platform. Hopefully we're building + * in uniprocessor mode. + */ +# define _ANDROID_MEMBAR_FULL_SMP() SMP_barrier_not_defined_for_platform() +#endif + + +/* + * Full barrier. On uniprocessors this is just a compiler reorder barrier, + * which ensures that the statements appearing above the barrier in the C/C++ + * code will be issued after the statements appearing below the barrier. + * + * For SMP this also includes a memory barrier instruction. On an ARM + * CPU this means that the current core will flush pending writes, wait + * for pending reads to complete, and discard any cached reads that could + * be stale. Other CPUs may do less, but the end result is equivalent. + */ +#if ANDROID_SMP != 0 +# define ANDROID_MEMBAR_FULL() _ANDROID_MEMBAR_FULL_SMP() +#else +# define ANDROID_MEMBAR_FULL() \ + do { __asm__ __volatile__ ("" ::: "memory"); } while (0) +#endif + +#ifdef __cplusplus +} // extern "C" +#endif + +#endif // BIONIC_ATOMIC_INLINE_H |