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| author | Andy McFadden <fadden@android.com> | 2010-05-19 22:38:07 -0700 |
|---|---|---|
| committer | Andy McFadden <fadden@android.com> | 2010-05-20 15:59:32 -0700 |
| commit | 4fdbadde921ec17b4ff9e97fbd41096903b21772 (patch) | |
| tree | 988de23c6495657f28fde4703ce656eb806e23cf | |
| parent | 8a1d2cf1422e35257c160ac5bb12dd3ee481c433 (diff) | |
| download | bionic-4fdbadde921ec17b4ff9e97fbd41096903b21772.zip bionic-4fdbadde921ec17b4ff9e97fbd41096903b21772.tar.gz bionic-4fdbadde921ec17b4ff9e97fbd41096903b21772.tar.bz2 | |
Atomic/SMP update.
Added an underscore to _ARM_HAVE_LDREX_STREX to make it match the others.
Added __ARM_HAVE_DMB and __ARM_HAVE_LDREXD when appropriate.
Fixed some typos.
Change-Id: I2f55febcff4aeb7de572a514fb2cd2f820dca27c
| -rw-r--r-- | libc/arch-arm/bionic/atomics_arm.S | 2 | ||||
| -rw-r--r-- | libc/arch-arm/include/machine/cpu-features.h | 24 |
2 files changed, 20 insertions, 6 deletions
diff --git a/libc/arch-arm/bionic/atomics_arm.S b/libc/arch-arm/bionic/atomics_arm.S index 047541f..f2e369d 100644 --- a/libc/arch-arm/bionic/atomics_arm.S +++ b/libc/arch-arm/bionic/atomics_arm.S @@ -142,7 +142,7 @@ __atomic_inc: /* r0(new) r1(addr) -> r0(old) */ /* replaced swp instruction with ldrex/strex for ARMv6 & ARMv7 */ __atomic_swap: -#if defined (_ARM_HAVE_LDREX_STREX) +#if defined (__ARM_HAVE_LDREX_STREX) 1: ldrex r2, [r1] strex r3, r0, [r1] teq r3, #0 diff --git a/libc/arch-arm/include/machine/cpu-features.h b/libc/arch-arm/include/machine/cpu-features.h index ecf6ff6..0f969fa 100644 --- a/libc/arch-arm/include/machine/cpu-features.h +++ b/libc/arch-arm/include/machine/cpu-features.h @@ -38,7 +38,7 @@ * IMPORTANT: We have no intention to support anything below an ARMv4T ! */ -/* _ARM_ARCH_REVISION is a number corresponding to the ARM revision +/* __ARM_ARCH__ is a number corresponding to the ARM revision * we're going to support * * it looks like our toolchain doesn't define __ARM_ARCH__ @@ -142,18 +142,32 @@ * * ldr pc, [<some address>] * - * note that this affects any instruction that explicitely changes the + * note that this affects any instruction that explicitly changes the * value of the pc register, including ldm { ...,pc } or 'add pc, #offset' */ #if __ARM_ARCH__ >= 5 # define __ARM_HAVE_PC_INTERWORK #endif -/* define _ARM_HAVE_LDREX_STREX for ARMv6 and ARMv7 architecure to be - * used in replacement of depricated swp instruction +/* define __ARM_HAVE_LDREX_STREX for ARMv6 and ARMv7 architecture to be + * used in replacement of deprecated swp instruction */ #if __ARM_ARCH__ >= 6 -# define _ARM_HAVE_LDREX_STREX +# define __ARM_HAVE_LDREX_STREX +#endif + +/* define __ARM_HAVE_DMB for ARMv7 architecture + */ +#if __ARM_ARCH__ >= 7 +# define __ARM_HAVE_DMB +#endif + +/* define __ARM_HAVE_LDREXD for ARMv7 architecture + * (also present in ARMv6K, but not implemented in ARMv7-M, neither of which + * we care about) + */ +#if __ARM_ARCH__ >= 7 +# define __ARM_HAVE_LDREXD #endif |