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authorGary King <gking@nvidia.com>2010-03-04 16:06:41 -0800
committerRicardo Cerqueira <cyanogenmod@cerqueira.org>2012-07-10 20:30:58 +0100
commitf225ebe43d596173f19e8d686f74b9a5fb1ff090 (patch)
tree43d0d706c9960591b60313a0912921deaeb43d12 /libc/private
parent4cf97a26fba5be1e08ce263740b4c7e45d6098fa (diff)
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implement work around for tegra errata 657451
tegra 2 processors have a bug in the register read path of bit 20 of the CP15 c13, 3 register (used for software thread local storage) the kernel work-around for this bug is to mux the value from bit 20 into bit 0; since the TLS value used by Android is an aligned address, bit 0 is known to be available. Change-Id: If70afa52585d327f9dd5eca479c14ca92532ddd8a Reviewed-on: http://git-master/r/773 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
Diffstat (limited to 'libc/private')
-rw-r--r--libc/private/bionic_tls.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/libc/private/bionic_tls.h b/libc/private/bionic_tls.h
index af19554..9a5146f 100644
--- a/libc/private/bionic_tls.h
+++ b/libc/private/bionic_tls.h
@@ -111,6 +111,12 @@ extern int __set_tls(void *ptr);
* Note that HAVE_ARM_TLS_REGISTER is build-specific
* (it must match your kernel configuration)
*/
+# ifdef HAVE_TEGRA_ERRATA_657451
+# define __munge_tls(_v) ( ((_v)&~((1ul<<20)|1ul)) | (((_v)&0x1)<<20) )
+# else
+# define __munge_tls(_v) (_v)
+#endif
+
# ifdef HAVE_ARM_TLS_REGISTER
/* We can read the address directly from a coprocessor
* register, which avoids touching the data cache
@@ -119,6 +125,7 @@ extern int __set_tls(void *ptr);
# define __get_tls() \
({ register unsigned int __val asm("r0"); \
asm ("mrc p15, 0, r0, c13, c0, 3" : "=r"(__val) ); \
+ __val = __munge_tls(__val); \
(volatile void*)__val; })
# else /* !HAVE_ARM_TLS_REGISTER */
/* The kernel provides the address of the TLS at a fixed