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| author | Brian Steuer <bsteuer@codeaurora.org> | 2009-12-11 12:36:25 -0800 |
|---|---|---|
| committer | Brian Steuer <bsteuer@codeaurora.org> | 2011-01-06 16:28:30 -0800 |
| commit | ff45fe786f94c3528255672f8a69a8c2d8811bfb (patch) | |
| tree | 7759781e2b2bba615c88721225d5fb14b4e2131f /libc | |
| parent | 9f00eee4dccfce04cfdfcd40fd59dc1ab54cf986 (diff) | |
| download | bionic-ff45fe786f94c3528255672f8a69a8c2d8811bfb.zip bionic-ff45fe786f94c3528255672f8a69a8c2d8811bfb.tar.gz bionic-ff45fe786f94c3528255672f8a69a8c2d8811bfb.tar.bz2 | |
bionic: remove V5 instruction for V6 targets
Instructions in memcpy that are only needed for ARMV5 targets
are now conditionally compiled for those targets.
Change-Id: I4c203bf43b6ea2df35f34f4a7917290f8463afc5
Diffstat (limited to 'libc')
| -rw-r--r-- | libc/arch-arm/bionic/memcpy.S | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/libc/arch-arm/bionic/memcpy.S b/libc/arch-arm/bionic/memcpy.S index ba55996..ace7cc5 100644 --- a/libc/arch-arm/bionic/memcpy.S +++ b/libc/arch-arm/bionic/memcpy.S @@ -260,20 +260,31 @@ cached_aligned32: * */ +#if __ARM_ARCH__ == 5 // Align the preload register to a cache-line because the cpu does // "critical word first" (the first word requested is loaded first). bic r12, r1, #0x1F add r12, r12, #64 +#endif 1: ldmia r1!, { r4-r11 } + +#if __ARM_ARCH__ == 5 PLD (r12, #64) +#else + PLD (r1, #64) +#endif + subs r2, r2, #32 +#if __ARM_ARCH__ == 5 // NOTE: if r12 is more than 64 ahead of r1, the following ldrhi // for ARM9 preload will not be safely guarded by the preceding subs. // When it is safely guarded the only possibility to have SIGSEGV here // is because the caller overstates the length. ldrhi r3, [r12], #32 /* cheap ARM9 preload */ +#endif + stmia r0!, { r4-r11 } bhs 1b |