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author | Elliott Hughes <enh@google.com> | 2014-11-26 19:31:19 -0800 |
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committer | Elliott Hughes <enh@google.com> | 2014-11-26 19:31:19 -0800 |
commit | 1b66f6e9d71dea78c2b1d1d24d92adad9d24ce5e (patch) | |
tree | 0ab7f6b2903442329aef6a68ec06f495e1f66a60 /libm | |
parent | 87516a6508add943cea99f3d29cb8bd89c4a3bdb (diff) | |
download | bionic-1b66f6e9d71dea78c2b1d1d24d92adad9d24ce5e.zip bionic-1b66f6e9d71dea78c2b1d1d24d92adad9d24ce5e.tar.gz bionic-1b66f6e9d71dea78c2b1d1d24d92adad9d24ce5e.tar.bz2 |
Move a private x86-64 header file out of the limelight.
Currently this is on everyone's include path and is getting exported
via the NDK.
Change-Id: Ia417839fb65c7e0afddcd9fae3438665dae8e752
Diffstat (limited to 'libm')
-rw-r--r-- | libm/include/amd64/machine/fpu.h | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/libm/include/amd64/machine/fpu.h b/libm/include/amd64/machine/fpu.h new file mode 100644 index 0000000..bda8f05 --- /dev/null +++ b/libm/include/amd64/machine/fpu.h @@ -0,0 +1,65 @@ +/* $OpenBSD: fpu.h,v 1.9 2011/03/23 16:54:34 pirofti Exp $ */ +/* $NetBSD: fpu.h,v 1.1 2003/04/26 18:39:40 fvdl Exp $ */ + +#ifndef _MACHINE_FPU_H_ +#define _MACHINE_FPU_H_ + +#include <sys/types.h> + +/* + * amd64 only uses the extended save/restore format used + * by fxsave/fsrestore, to always deal with the SSE registers, + * which are part of the ABI to pass floating point values. + * Must be stored in memory on a 16-byte boundary. + */ + +struct fxsave64 { + u_int16_t fx_fcw; + u_int16_t fx_fsw; + u_int8_t fx_ftw; + u_int8_t fx_unused1; + u_int16_t fx_fop; + u_int64_t fx_rip; + u_int64_t fx_rdp; + u_int32_t fx_mxcsr; + u_int32_t fx_mxcsr_mask; + u_int64_t fx_st[8][2]; /* 8 normal FP regs */ + u_int64_t fx_xmm[16][2]; /* 16 SSE2 registers */ + u_int8_t fx_unused3[96]; +} __packed; + +struct savefpu { + struct fxsave64 fp_fxsave; /* see above */ + u_int16_t fp_ex_sw; /* saved status from last exception */ + u_int16_t fp_ex_tw; /* saved tag from last exception */ +}; + +/* + * The i387 defaults to Intel extended precision mode and round to nearest, + * with all exceptions masked. + */ +#define __INITIAL_NPXCW__ 0x037f +#define __INITIAL_MXCSR__ 0x1f80 +#define __INITIAL_MXCSR_MASK__ 0xffbf + +#ifdef _KERNEL +/* + * XXX + */ +struct trapframe; +struct cpu_info; + +extern uint32_t fpu_mxcsr_mask; + +void fpuinit(struct cpu_info *); +void fpudrop(void); +void fpudiscard(struct proc *); +void fputrap(struct trapframe *); +void fpusave_proc(struct proc *, int); +void fpusave_cpu(struct cpu_info *, int); +void fpu_kernel_enter(void); +void fpu_kernel_exit(void); + +#endif + +#endif /* _MACHINE_FPU_H_ */ |