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-rw-r--r--libc/arch-arm/bionic/memcpy.S13
1 files changed, 12 insertions, 1 deletions
diff --git a/libc/arch-arm/bionic/memcpy.S b/libc/arch-arm/bionic/memcpy.S
index ba55996..b8d1007 100644
--- a/libc/arch-arm/bionic/memcpy.S
+++ b/libc/arch-arm/bionic/memcpy.S
@@ -38,7 +38,7 @@
.align 4
/* a prefetch distance of 4 cache-lines works best experimentally */
-#define CACHE_LINE_SIZE 64
+#define CACHE_LINE_SIZE 32
#define PREFETCH_DISTANCE (CACHE_LINE_SIZE*4)
memcpy:
@@ -260,20 +260,31 @@ cached_aligned32:
*
*/
+#if __ARM_ARCH__ == 5
// Align the preload register to a cache-line because the cpu does
// "critical word first" (the first word requested is loaded first).
bic r12, r1, #0x1F
add r12, r12, #64
+#endif
1: ldmia r1!, { r4-r11 }
+
+#if __ARM_ARCH__ == 5
PLD (r12, #64)
+#else
+ PLD (r1, #64)
+#endif
+
subs r2, r2, #32
+#if __ARM_ARCH__ == 5
// NOTE: if r12 is more than 64 ahead of r1, the following ldrhi
// for ARM9 preload will not be safely guarded by the preceding subs.
// When it is safely guarded the only possibility to have SIGSEGV here
// is because the caller overstates the length.
ldrhi r3, [r12], #32 /* cheap ARM9 preload */
+#endif
+
stmia r0!, { r4-r11 }
bhs 1b