diff options
Diffstat (limited to 'libc/arch-mips64')
215 files changed, 7861 insertions, 0 deletions
diff --git a/libc/arch-mips64/bionic/__bionic_clone.S b/libc/arch-mips64/bionic/__bionic_clone.S new file mode 100644 index 0000000..0d266ee --- /dev/null +++ b/libc/arch-mips64/bionic/__bionic_clone.S @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> +#include <linux/errno.h> +#include <linux/sched.h> + +#if (_MIPS_SIM == _ABIO32) || (_MIPS_SIM == _ABI32) +FRAMESZ = MKFSIZ(NARGSAVE,0) +FRAME_ARG = 0*REGSZ +FRAME_FN = 1*REGSZ +#else +FRAMESZ = MKFSIZ(0,3) +FRAME_GP = FRAMESZ-1*REGSZ +FRAME_ARG = FRAMESZ-2*REGSZ +FRAME_FN = FRAMESZ-3*REGSZ +#endif + +// pid_t __bionic_clone(int flags, void* child_stack, pid_t* parent_tid, void* tls, pid_t* child_tid, int (*fn)(void*), void* arg); +LEAF(__bionic_clone, FRAMESZ) + PTR_SUBU sp, FRAMESZ # allocate stack frame + SETUP_GP64(FRAME_GP,__bionic_clone) + SAVE_GP(FRAME_GP) + + # set up child stack + PTR_SUBU a1,FRAMESZ +#if (_MIPS_SIM == _ABIO32) || (_MIPS_SIM == _ABI32) + PTR_L t0,FRAMESZ+5*REGSZ(sp) # fn + PRL_L t1,FRAMESZ+6*REGSZ(sp) # arg + PTR_S t0,FRAME_FN(a1) # fn + PTR_S t1,FRAME_ARG(a1) # arg +#else + PTR_L t0,FRAME_GP(sp) # copy gp to child stack + PTR_S t0,FRAME_GP(a1) + PTR_S a5,FRAME_FN(a1) # fn + PTR_S a6,FRAME_ARG(a1) # arg +# endif + + # remainder of arguments are correct for clone system call + LI v0,__NR_clone + syscall + + move a0,v0 + bnez a3,.L__error_bc + + beqz v0,.L__thread_start_bc + + RESTORE_GP64 + PTR_ADDU sp,FRAMESZ + j ra + +.L__thread_start_bc: + # Clear return address in child so we don't unwind further. + li ra,0 + + # void __start_thread(int (*func)(void*), void *arg) + PTR_L a0,FRAME_FN(sp) # fn + PTR_L a1,FRAME_ARG(sp) # arg + LA t9,__start_thread + RESTORE_GP64 + /* + * For O32 etc the child stack must have space for a0..a3 to be stored + * For N64 etc, the child stack can be restored to the original value + */ +#if !((_MIPS_SIM == _ABIO32) || (_MIPS_SIM == _ABI32)) + PTR_ADDU sp,FRAMESZ +#endif + j t9 + +.L__error_bc: + LA t9,__set_errno_internal + RESTORE_GP64 + PTR_ADDU sp,FRAMESZ + j t9 + END(__bionic_clone) +.hidden __bionic_clone diff --git a/libc/arch-mips64/bionic/_exit_with_stack_teardown.S b/libc/arch-mips64/bionic/_exit_with_stack_teardown.S new file mode 100644 index 0000000..fcf8cc1 --- /dev/null +++ b/libc/arch-mips64/bionic/_exit_with_stack_teardown.S @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + +// void _exit_with_stack_teardown(void* stackBase, size_t stackSize) +ENTRY_PRIVATE(_exit_with_stack_teardown) + li v0, __NR_munmap + syscall + // If munmap failed, we ignore the failure and exit anyway. + + li a0, 0 + li v0, __NR_exit + syscall + // The exit syscall does not return. +END(_exit_with_stack_teardown) diff --git a/libc/arch-mips64/bionic/_setjmp.S b/libc/arch-mips64/bionic/_setjmp.S new file mode 100644 index 0000000..d237e6d --- /dev/null +++ b/libc/arch-mips64/bionic/_setjmp.S @@ -0,0 +1,150 @@ +/* $OpenBSD: _setjmp.S,v 1.4 2005/08/07 16:40:15 espie Exp $ */ + +/* + * Copyright (c) 2002 Opsycon AB (www.opsycon.se / www.opsycon.com) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Opsycon AB nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#include <private/bionic_asm.h> +#include <machine/regnum.h> +#include <machine/signal.h> + +/* + * _setjmp, _longjmp (not restoring signal state) + * + * XXX FPSET should probably be taken from SR setting. hmmm... + * GPOFF and FRAMESIZE must be the same for both _setjmp and _longjmp! + * + */ + +FRAMESZ= MKFSIZ(0,4) +GPOFF= FRAMESZ-2*REGSZ + +LEAF(_setjmp, FRAMESZ) + PTR_SUBU sp, FRAMESZ + SETUP_GP64(GPOFF, _setjmp) + SAVE_GP(GPOFF) + .set noreorder +#if defined(__mips64) + dli v0, 0xACEDBADE # sigcontext magic number +#else + li v0, 0xACEDBADE # sigcontext magic number +#endif + REG_S v0, SC_REGS+ZERO*REGSZ(a0) + REG_S s0, SC_REGS+S0*REGSZ(a0) + REG_S s1, SC_REGS+S1*REGSZ(a0) + REG_S s2, SC_REGS+S2*REGSZ(a0) + REG_S s3, SC_REGS+S3*REGSZ(a0) + REG_S s4, SC_REGS+S4*REGSZ(a0) + REG_S s5, SC_REGS+S5*REGSZ(a0) + REG_S s6, SC_REGS+S6*REGSZ(a0) + REG_S s7, SC_REGS+S7*REGSZ(a0) + REG_S s8, SC_REGS+S8*REGSZ(a0) + REG_L v0, GPOFF(sp) + REG_S v0, SC_REGS+GP*REGSZ(a0) + PTR_ADDU v0, sp, FRAMESZ + REG_S v0, SC_REGS+SP*REGSZ(a0) + REG_S ra, SC_PC(a0) + +#if !defined(SOFTFLOAT) + li v0, 1 # be nice if we could tell + REG_S v0, SC_FPUSED(a0) # sc_fpused = 1 + cfc1 v0, $31 + s.d $f20, SC_FPREGS+((F20-F0)*REGSZ_FP)(a0) + s.d $f22, SC_FPREGS+((F22-F0)*REGSZ_FP)(a0) + s.d $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0) + s.d $f26, SC_FPREGS+((F26-F0)*REGSZ_FP)(a0) + s.d $f28, SC_FPREGS+((F28-F0)*REGSZ_FP)(a0) + s.d $f30, SC_FPREGS+((F30-F0)*REGSZ_FP)(a0) +#if _MIPS_FPSET == 32 + s.d $f21, SC_FPREGS+((F21-F0)*REGSZ_FP)(a0) + s.d $f23, SC_FPREGS+((F23-F0)*REGSZ_FP)(a0) + s.d $f25, SC_FPREGS+((F25-F0)*REGSZ_FP)(a0) + s.d $f27, SC_FPREGS+((F27-F0)*REGSZ_FP)(a0) + s.d $f29, SC_FPREGS+((F29-F0)*REGSZ_FP)(a0) + s.d $f31, SC_FPREGS+((F31-F0)*REGSZ_FP)(a0) +#endif + REG_S v0, SC_FPREGS+((FSR-F0)*REGSZ)(a0) +#endif /* !SOFTFLOAT */ + RESTORE_GP64 + PTR_ADDU sp, FRAMESZ + j ra + move v0, zero +END(_setjmp) + +LEAF(_longjmp, FRAMESZ) + PTR_SUBU sp, FRAMESZ + SETUP_GP64(GPOFF, _longjmp) + SAVE_GP(GPOFF) + .set noreorder + REG_L v0, SC_REGS+ZERO*REGSZ(a0) + bne v0, 0xACEDBADE, botch # jump if error + REG_L ra, SC_PC(a0) + REG_L v0, SC_FPREGS+((FSR-F0)*REGSZ)(a0) + REG_L s0, SC_REGS+S0*REGSZ(a0) + REG_L s1, SC_REGS+S1*REGSZ(a0) + REG_L s2, SC_REGS+S2*REGSZ(a0) + REG_L s3, SC_REGS+S3*REGSZ(a0) + REG_L s4, SC_REGS+S4*REGSZ(a0) + REG_L s5, SC_REGS+S5*REGSZ(a0) + REG_L s6, SC_REGS+S6*REGSZ(a0) + REG_L s7, SC_REGS+S7*REGSZ(a0) + REG_L s8, SC_REGS+S8*REGSZ(a0) + REG_L gp, SC_REGS+GP*REGSZ(a0) + REG_L sp, SC_REGS+SP*REGSZ(a0) +#if !defined(SOFTFLOAT) + ctc1 v0, $31 + l.d $f20, SC_FPREGS+((F20-F0)*REGSZ_FP)(a0) + l.d $f22, SC_FPREGS+((F22-F0)*REGSZ_FP)(a0) + l.d $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0) + l.d $f26, SC_FPREGS+((F26-F0)*REGSZ_FP)(a0) + l.d $f28, SC_FPREGS+((F28-F0)*REGSZ_FP)(a0) + l.d $f30, SC_FPREGS+((F30-F0)*REGSZ_FP)(a0) +#if _MIPS_FPSET == 32 + l.d $f21, SC_FPREGS+((F21-F0)*REGSZ_FP)(a0) + l.d $f23, SC_FPREGS+((F23-F0)*REGSZ_FP)(a0) + l.d $f25, SC_FPREGS+((F25-F0)*REGSZ_FP)(a0) + l.d $f27, SC_FPREGS+((F27-F0)*REGSZ_FP)(a0) + l.d $f29, SC_FPREGS+((F29-F0)*REGSZ_FP)(a0) + l.d $f31, SC_FPREGS+((F31-F0)*REGSZ_FP)(a0) +#endif +#endif /* !SOFTFLOAT */ + bne a1, zero, 1f + nop + li a1, 1 # never return 0! +1: + j ra + move v0, a1 + +botch: + jal longjmperror + nop + jal abort + nop + RESTORE_GP64 + PTR_ADDU sp, FRAMESZ +END(_longjmp) diff --git a/libc/arch-mips64/bionic/atexit.h b/libc/arch-mips64/bionic/atexit.h new file mode 100644 index 0000000..759008c --- /dev/null +++ b/libc/arch-mips64/bionic/atexit.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +extern void *__dso_handle; +extern int __cxa_atexit(void (*func)(void *), void *arg, void *dso); + +__attribute__ ((visibility ("hidden"))) +int atexit(void (*func)(void)) +{ + return (__cxa_atexit((void (*)(void *))func, (void *)0, &__dso_handle)); +} diff --git a/libc/arch-mips64/bionic/crtbegin.c b/libc/arch-mips64/bionic/crtbegin.c new file mode 100644 index 0000000..2ea31ad --- /dev/null +++ b/libc/arch-mips64/bionic/crtbegin.c @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include "../../bionic/libc_init_common.h" +#include <stddef.h> +#include <stdint.h> + +__attribute__ ((section (".preinit_array"))) +void (*__PREINIT_ARRAY__)(void) = (void (*)(void)) -1; + +__attribute__ ((section (".init_array"))) +void (*__INIT_ARRAY__)(void) = (void (*)(void)) -1; + +__attribute__ ((section (".fini_array"))) +void (*__FINI_ARRAY__)(void) = (void (*)(void)) -1; + + +__LIBC_HIDDEN__ void do_mips_start(void *raw_args) { + structors_array_t array; + array.preinit_array = &__PREINIT_ARRAY__; + array.init_array = &__INIT_ARRAY__; + array.fini_array = &__FINI_ARRAY__; + + __libc_init(raw_args, NULL, &main, &array); +} + +/* + * This function prepares the return address with a branch-and-link + * instruction (bal) and then uses a .cpsetup to compute the Global + * Offset Table (GOT) pointer ($gp). The $gp is then used to load + * the address of _do_mips_start() into $t9 just before calling it. + * Terminating the stack with a NULL return address. + */ +__asm__ ( +" .set push \n" +" \n" +" .text \n" +" .align 4 \n" +" .type __start,@function \n" +" .globl __start \n" +" .globl _start \n" +" \n" +" .ent __start \n" +"__start: \n" +" _start: \n" +" .frame $sp,32,$0 \n" +" .mask 0x80000000,-8 \n" +" \n" +" move $a0, $sp \n" +" daddiu $sp, $sp, -32 \n" +" \n" +" .set noreorder \n" +" bal 1f \n" +" nop \n" +"1: \n" +" .cpsetup $ra,16,1b \n" +" .set reorder \n" +" \n" +" sd $0, 24($sp) \n" +" jal do_mips_start \n" +" \n" +"2: b 2b \n" +" .end __start \n" +" \n" +" .set pop \n" +); + +#include "../../arch-common/bionic/__dso_handle.h" +#include "atexit.h" diff --git a/libc/arch-mips64/bionic/crtbegin_so.c b/libc/arch-mips64/bionic/crtbegin_so.c new file mode 100644 index 0000000..d664ce6 --- /dev/null +++ b/libc/arch-mips64/bionic/crtbegin_so.c @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +extern void __cxa_finalize(void *); +extern void *__dso_handle; + +__attribute__((visibility("hidden"),destructor)) +void __on_dlclose() { + __cxa_finalize(&__dso_handle); +} + +#include "../../arch-common/bionic/__dso_handle_so.h" +#include "atexit.h" diff --git a/libc/arch-mips64/bionic/setjmp.S b/libc/arch-mips64/bionic/setjmp.S new file mode 100644 index 0000000..31786be --- /dev/null +++ b/libc/arch-mips64/bionic/setjmp.S @@ -0,0 +1,174 @@ +/* $OpenBSD: setjmp.S,v 1.5 2005/08/07 16:40:15 espie Exp $ */ + +/* + * Copyright (c) 2001-2002 Opsycon AB (www.opsycon.se / www.opsycon.com) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of Opsycon AB nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#include <private/bionic_asm.h> +#include <machine/regnum.h> +#include <machine/signal.h> + +/* + * setjmp, longjmp implementation for libc. this code depends + * on the layout of the struct sigcontext in machine/signal.h. + * + */ + +FRAMESZ= MKFSIZ(2,6) +A1OFF= FRAMESZ-4*REGSZ +A0OFF= FRAMESZ-3*REGSZ +GPOFF= FRAMESZ-2*REGSZ +RAOFF= FRAMESZ-1*REGSZ + +NON_LEAF(setjmp, FRAMESZ, ra) + .mask 0x80000000, RAOFF + PTR_SUBU sp, FRAMESZ # allocate stack frame + SETUP_GP64(GPOFF, setjmp) + SAVE_GP(GPOFF) + .set reorder + REG_S ra, RAOFF(sp) # save state + REG_S a0, A0OFF(sp) + + move a0, zero # get current signal mask + jal sigblock + + REG_L v1, A0OFF(sp) # v1 = jmpbuf + REG_S v0, SC_MASK(v1) # save sc_mask = sigblock(0) + + REG_L a0, A0OFF(sp) # restore jmpbuf + REG_L ra, RAOFF(sp) + REG_S ra, SC_PC(a0) # sc_pc = return address +#if defined(__mips64) + dli v0, 0xACEDBADE # sigcontext magic number +#else + li v0, 0xACEDBADE # sigcontext magic number +#endif + REG_S v0, SC_REGS+ZERO*REGSZ(a0) + REG_S s0, SC_REGS+S0*REGSZ(a0) + REG_S s1, SC_REGS+S1*REGSZ(a0) + REG_S s2, SC_REGS+S2*REGSZ(a0) + REG_S s3, SC_REGS+S3*REGSZ(a0) + REG_S s4, SC_REGS+S4*REGSZ(a0) + REG_S s5, SC_REGS+S5*REGSZ(a0) + REG_S s6, SC_REGS+S6*REGSZ(a0) + REG_S s7, SC_REGS+S7*REGSZ(a0) + REG_S s8, SC_REGS+S8*REGSZ(a0) + REG_L v0, GPOFF(sp) + REG_S v0, SC_REGS+GP*REGSZ(a0) + PTR_ADDU v0, sp, FRAMESZ + REG_S v0, SC_REGS+SP*REGSZ(a0) + +#if !defined(SOFTFLOAT) + li v0, 1 # be nice if we could tell + REG_S v0, SC_FPUSED(a0) # sc_fpused = 1 + cfc1 v0, $31 + s.d $f20, SC_FPREGS+((F20-F0)*REGSZ_FP)(a0) + s.d $f22, SC_FPREGS+((F22-F0)*REGSZ_FP)(a0) + s.d $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0) + s.d $f26, SC_FPREGS+((F26-F0)*REGSZ_FP)(a0) + s.d $f28, SC_FPREGS+((F28-F0)*REGSZ_FP)(a0) + s.d $f30, SC_FPREGS+((F30-F0)*REGSZ_FP)(a0) +#if _MIPS_FPSET == 32 + s.d $f21, SC_FPREGS+((F21-F0)*REGSZ_FP)(a0) + s.d $f23, SC_FPREGS+((F23-F0)*REGSZ_FP)(a0) + s.d $f25, SC_FPREGS+((F25-F0)*REGSZ_FP)(a0) + s.d $f27, SC_FPREGS+((F27-F0)*REGSZ_FP)(a0) + s.d $f29, SC_FPREGS+((F29-F0)*REGSZ_FP)(a0) + s.d $f31, SC_FPREGS+((F31-F0)*REGSZ_FP)(a0) +#endif + REG_S v0, SC_FPREGS+((FSR-F0)*REGSZ)(a0) +#endif /* !SOFTFLOAT */ + move v0, zero + RESTORE_GP64 + PTR_ADDU sp, FRAMESZ + j ra + +botch: + jal longjmperror + jal abort + RESTORE_GP64 + PTR_ADDU sp, FRAMESZ +END(setjmp) + + +LEAF(longjmp, FRAMESZ) + PTR_SUBU sp, FRAMESZ + SETUP_GP64(GPOFF, longjmp) + SAVE_GP(GPOFF) + .set reorder + sw a1, A1OFF(sp) + sw a0, A0OFF(sp) + + lw a0, SC_MASK(a0) + jal sigsetmask + + lw a0, A0OFF(sp) + lw a1, A1OFF(sp) + + .set noreorder + REG_L v0, SC_REGS+ZERO*REGSZ(a0) + bne v0, 0xACEDBADE, botch # jump if error + REG_L ra, SC_PC(a0) + REG_L s0, SC_REGS+S0*REGSZ(a0) + REG_L s1, SC_REGS+S1*REGSZ(a0) + REG_L s2, SC_REGS+S2*REGSZ(a0) + REG_L s3, SC_REGS+S3*REGSZ(a0) + REG_L s4, SC_REGS+S4*REGSZ(a0) + REG_L s5, SC_REGS+S5*REGSZ(a0) + REG_L s6, SC_REGS+S6*REGSZ(a0) + REG_L s7, SC_REGS+S7*REGSZ(a0) + REG_L s8, SC_REGS+S8*REGSZ(a0) + REG_L gp, SC_REGS+GP*REGSZ(a0) + REG_L sp, SC_REGS+SP*REGSZ(a0) + +#if !defined(SOFTFLOAT) + REG_L v0, SC_FPREGS+((FSR-F0)*REGSZ)(a0) + ctc1 v0, $31 + l.d $f20, SC_FPREGS+((F20-F0)*REGSZ_FP)(a0) + l.d $f22, SC_FPREGS+((F22-F0)*REGSZ_FP)(a0) + l.d $f24, SC_FPREGS+((F24-F0)*REGSZ_FP)(a0) + l.d $f26, SC_FPREGS+((F26-F0)*REGSZ_FP)(a0) + l.d $f28, SC_FPREGS+((F28-F0)*REGSZ_FP)(a0) + l.d $f30, SC_FPREGS+((F30-F0)*REGSZ_FP)(a0) +#if _MIPS_FPSET == 32 + l.d $f21, SC_FPREGS+((F21-F0)*REGSZ_FP)(a0) + l.d $f23, SC_FPREGS+((F23-F0)*REGSZ_FP)(a0) + l.d $f25, SC_FPREGS+((F25-F0)*REGSZ_FP)(a0) + l.d $f27, SC_FPREGS+((F27-F0)*REGSZ_FP)(a0) + l.d $f29, SC_FPREGS+((F29-F0)*REGSZ_FP)(a0) + l.d $f31, SC_FPREGS+((F31-F0)*REGSZ_FP)(a0) +#endif +#endif /* !SOFTFLOAT */ + bne a1, zero, 1f + nop + li a1, 1 # never return 0! +1: + j ra + move v0, a1 + +END(longjmp) diff --git a/libc/arch-mips64/bionic/sigsetjmp.S b/libc/arch-mips64/bionic/sigsetjmp.S new file mode 100644 index 0000000..9d2e5ea --- /dev/null +++ b/libc/arch-mips64/bionic/sigsetjmp.S @@ -0,0 +1,77 @@ +/* $OpenBSD: sigsetjmp.S,v 1.5 2005/08/07 16:40:15 espie Exp $ */ +/*- + * Copyright (c) 1991, 1993, 1995, + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Havard Eidnes. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> +#include <machine/regnum.h> +#include <machine/setjmp.h> + +/* + * trampolines for sigsetjmp and siglongjmp save and restore mask. + * + */ +FRAMESZ= MKFSIZ(1,1) +GPOFF= FRAMESZ-2*REGSZ + +LEAF(sigsetjmp, FRAMESZ) + PTR_SUBU sp, FRAMESZ + SETUP_GP64(GPOFF, sigsetjmp) + .set reorder + REG_S a1, (_JBLEN*REGSZ)(a0) # save "savemask" + bne a1, 0x0, 1f # do saving of signal mask? + LA t9, _setjmp + RESTORE_GP64 + PTR_ADDU sp, FRAMESZ + jr t9 + +1: LA t9, setjmp + RESTORE_GP64 + PTR_ADDU sp, FRAMESZ + jr t9 +END(sigsetjmp) + +LEAF(siglongjmp, FRAMESZ) + PTR_SUBU sp, FRAMESZ + SETUP_GP64(GPOFF, siglongjmp) + .set reorder + REG_L t0, (_JBLEN*REGSZ)(a0) # get "savemask" + bne t0, 0x0, 1f # restore signal mask? + LA t9, _longjmp + RESTORE_GP64 + PTR_ADDU sp, FRAMESZ + jr t9 +1: + LA t9, longjmp + RESTORE_GP64 + PTR_ADDU sp, FRAMESZ + jr t9 +END(siglongjmp) diff --git a/libc/arch-mips64/bionic/syscall.S b/libc/arch-mips64/bionic/syscall.S new file mode 100644 index 0000000..924741d --- /dev/null +++ b/libc/arch-mips64/bionic/syscall.S @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2013 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> + +#if (_MIPS_SIM == _ABIO32) || (_MIPS_SIM == _ABI32) +FRAMESZ = MKFSIZ(6,0) +#else +FRAMESZ = MKFSIZ(0,1) +FRAME_GP = FRAMESZ-1*REGSZ +#endif + +LEAF(syscall,FRAMESZ) + PTR_SUBU sp, FRAMESZ # allocate stack frame + SETUP_GP64(FRAME_GP,syscall) + SAVE_GP(FRAME_GP) + move v0, a0 # syscall number to v0 + move a0, a1 # shift args down + move a1, a2 + move a2, a3 +#if (_MIPS_SIM == _ABIO32) || (_MIPS_SIM == _ABI32) + REG_L a3, FRAMESZ+4*REGSZ(sp) + REG_L t0, FRAMESZ+5*REGSZ(sp) + REG_L t1, FRAMESZ+6*REGSZ(sp) + REG_S t0, 4*REGSZ(sp) + REG_S t1, 5*REGSZ(sp) +#else + move a3, a4 + move a4, a5 + REG_L a5, FRAMESZ(sp) +#endif + syscall + move a0, v0 + bnez a3, 1f + RESTORE_GP64 + PTR_ADDU sp, FRAMESZ + j ra +1: + LA t9,__set_errno_internal + RESTORE_GP64 + PTR_ADDU sp, FRAMESZ + j t9 + END(syscall) diff --git a/libc/arch-mips64/bionic/vfork.S b/libc/arch-mips64/bionic/vfork.S new file mode 100644 index 0000000..d180a8c --- /dev/null +++ b/libc/arch-mips64/bionic/vfork.S @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2008 The Android Open Source Project + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <private/bionic_asm.h> +#include <linux/sched.h> + +// TODO: mips' uapi signal.h is missing #ifndef __ASSEMBLY__. +// #include <asm/signal.h> +#define SIGCHLD 18 + + .text + +#if (_MIPS_SIM == _ABIO32) || (_MIPS_SIM == _ABI32) +FRAMESZ = MKFSIZ(5,0) +#else +FRAMESZ = MKFSIZ(0,0) +#endif + +LEAF(vfork,FRAMESZ) +#if FRAMESZ!=0 + PTR_SUBU sp, FRAMESZ +#endif + SETUP_GP64(a5, vfork) + LI a0, (CLONE_VM | CLONE_VFORK | SIGCHLD) + move a1, $0 + move a2, $0 + move a3, $0 +#if (_MIPS_SIM == _ABIO32) || (_MIPS_SIM == _ABI32) + REG_S $0, 4*REGSZ(sp) +#else + move a4, $0 +#endif + LI v0, __NR_clone + syscall +#if FRAMESZ!=0 + PTR_ADDU sp,FRAMESZ +#endif + move a0, v0 + bnez a3, 1f + RESTORE_GP64 + j ra +1: + LA t9,__set_errno_internal + RESTORE_GP64 + j t9 + END(vfork) diff --git a/libc/arch-mips64/include/machine/asm.h b/libc/arch-mips64/include/machine/asm.h new file mode 100644 index 0000000..5eacde3 --- /dev/null +++ b/libc/arch-mips64/include/machine/asm.h @@ -0,0 +1,208 @@ +/* $OpenBSD: asm.h,v 1.7 2004/10/20 12:49:15 pefo Exp $ */ + +/* + * Copyright (c) 2001-2002 Opsycon AB (www.opsycon.se / www.opsycon.com) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ +#ifndef _MIPS64_ASM_H +#define _MIPS64_ASM_H + +#ifndef _ALIGN_TEXT +# define _ALIGN_TEXT .align 4 +#endif + +#undef __bionic_asm_custom_entry +#undef __bionic_asm_custom_end +#define __bionic_asm_custom_entry(f) .ent f +#define __bionic_asm_custom_end(f) .end f + +#include <machine/regdef.h> + +#define _MIPS_ISA_MIPS1 1 /* R2000/R3000 */ +#define _MIPS_ISA_MIPS2 2 /* R4000/R6000 */ +#define _MIPS_ISA_MIPS3 3 /* R4000 */ +#define _MIPS_ISA_MIPS4 4 /* TFP (R1x000) */ +#define _MIPS_ISA_MIPS5 5 +#define _MIPS_ISA_MIPS32 6 +#define _MIPS_ISA_MIPS64 7 + +#if !defined(ABICALLS) && !defined(_NO_ABICALLS) +#define ABICALLS .abicalls +#endif + +#if defined(ABICALLS) && !defined(_KERNEL) + ABICALLS +#endif + +#if !defined(__MIPSEL__) && !defined(__MIPSEB__) +#error "__MIPSEL__ or __MIPSEB__ must be defined" +#endif +/* + * Define how to access unaligned data word + */ +#if defined(__MIPSEL__) +#define LWLO lwl +#define LWHI lwr +#define SWLO swl +#define SWHI swr +#define LDLO ldl +#define LDHI ldr +#define SDLO sdl +#define SDHI sdr +#endif +#if defined(__MIPSEB__) +#define LWLO lwr +#define LWHI lwl +#define SWLO swr +#define SWHI swl +#define LDLO ldr +#define LDHI ldl +#define SDLO sdr +#define SDHI sdl +#endif + +/* + * Define programming environment for ABI. + */ +#if defined(ABICALLS) && !defined(_KERNEL) && !defined(_STANDALONE) + +#if (_MIPS_SIM == _ABIO32) || (_MIPS_SIM == _ABI32) +#define NARGSAVE 4 + +#define SETUP_GP \ + .set noreorder; \ + .cpload t9; \ + .set reorder; + +#define SAVE_GP(x) \ + .cprestore x + +#define SETUP_GP64(gpoff, name) +#define RESTORE_GP64 +#endif + +#if (_MIPS_SIM == _ABI64) || (_MIPS_SIM == _ABIN32) +#define NARGSAVE 0 + +#define SETUP_GP +#define SAVE_GP(x) +#define SETUP_GP64(gpoff, name) \ + .cpsetup t9, gpoff, name +#define RESTORE_GP64 \ + .cpreturn +#endif + +#define MKFSIZ(narg,locals) (((narg+locals)*REGSZ+31)&(~31)) + +#else /* defined(ABICALLS) && !defined(_KERNEL) */ + +#define NARGSAVE 4 +#define SETUP_GP +#define SAVE_GP(x) + +#define ALIGNSZ 16 /* Stack layout alignment */ +#define FRAMESZ(sz) (((sz) + (ALIGNSZ-1)) & ~(ALIGNSZ-1)) + +#endif + +/* + * Basic register operations based on selected ISA + */ +#if (_MIPS_ISA == _MIPS_ISA_MIPS1 || _MIPS_ISA == _MIPS_ISA_MIPS2 || _MIPS_ISA == _MIPS_ISA_MIPS32) +#define REGSZ 4 /* 32 bit mode register size */ +#define LOGREGSZ 2 /* log rsize */ +#define REG_S sw +#define REG_L lw +#define CF_SZ 24 /* Call frame size */ +#define CF_ARGSZ 16 /* Call frame arg size */ +#define CF_RA_OFFS 20 /* Call ra save offset */ +#endif + +#if (_MIPS_ISA == _MIPS_ISA_MIPS3 || _MIPS_ISA == _MIPS_ISA_MIPS4 || _MIPS_ISA == _MIPS_ISA_MIPS64) +#define REGSZ 8 /* 64 bit mode register size */ +#define LOGREGSZ 3 /* log rsize */ +#define REG_S sd +#define REG_L ld +#define CF_SZ 48 /* Call frame size (multiple of ALIGNSZ) */ +#define CF_ARGSZ 32 /* Call frame arg size */ +#define CF_RA_OFFS 40 /* Call ra save offset */ +#endif + +#define REGSZ_FP 8 /* 64 bit FP register size */ + +#ifndef __LP64__ +#define PTR_L lw +#define PTR_S sw +#define PTR_SUB sub +#define PTR_ADD add +#define PTR_SUBU subu +#define PTR_ADDU addu +#define LI li +#define LA la +#define PTR_SLL sll +#define PTR_SRL srl +#define PTR_VAL .word +#else +#define PTR_L ld +#define PTR_S sd +#define PTR_ADD dadd +#define PTR_SUB dsub +#define PTR_SUBU dsubu +#define PTR_ADDU daddu +#define LI dli +#define LA dla +#define PTR_SLL dsll +#define PTR_SRL dsrl +#define PTR_VAL .dword +#endif + +/* + * LEAF(x, fsize) + * + * Declare a leaf routine. + */ +#define LEAF(x, fsize) \ + .align 3; \ + .globl x; \ + .ent x, 0; \ +x: ; \ + .cfi_startproc; \ + .frame sp, fsize, ra; \ + SETUP_GP \ + +/* + * NON_LEAF(x) + * + * Declare a non-leaf routine (a routine that makes other C calls). + */ +#define NON_LEAF(x, fsize, retpc) \ + .align 3; \ + .globl x; \ + .ent x, 0; \ +x: ; \ + .cfi_startproc; \ + .frame sp, fsize, retpc; \ + SETUP_GP \ + +#endif /* !_MIPS_ASM_H */ diff --git a/libc/arch-mips64/include/machine/elf_machdep.h b/libc/arch-mips64/include/machine/elf_machdep.h new file mode 100644 index 0000000..d27d431 --- /dev/null +++ b/libc/arch-mips64/include/machine/elf_machdep.h @@ -0,0 +1,196 @@ +/* $NetBSD: elf_machdep.h,v 1.15 2011/03/15 07:39:22 matt Exp $ */ + +#ifndef _MIPS_ELF_MACHDEP_H_ +#define _MIPS_ELF_MACHDEP_H_ + +#ifdef _LP64 +#define ARCH_ELFSIZE 64 /* MD native binary size */ +#else +#define ARCH_ELFSIZE 32 /* MD native binary size */ +#endif + +#if ELFSIZE == 32 +#define ELF32_MACHDEP_ID_CASES \ + case EM_MIPS: \ + break; + +#define ELF32_MACHDEP_ID EM_MIPS +#elif ELFSIZE == 64 +#define ELF64_MACHDEP_ID_CASES \ + case EM_MIPS: \ + break; + +#define ELF64_MACHDEP_ID EM_MIPS +#endif + +/* mips relocs. */ + +#define R_MIPS_NONE 0 +#define R_MIPS_16 1 +#define R_MIPS_32 2 +#define R_MIPS_REL32 3 +#define R_MIPS_REL R_MIPS_REL32 +#define R_MIPS_26 4 +#define R_MIPS_HI16 5 /* high 16 bits of symbol value */ +#define R_MIPS_LO16 6 /* low 16 bits of symbol value */ +#define R_MIPS_GPREL16 7 /* GP-relative reference */ +#define R_MIPS_LITERAL 8 /* Reference to literal section */ +#define R_MIPS_GOT16 9 /* Reference to global offset table */ +#define R_MIPS_GOT R_MIPS_GOT16 +#define R_MIPS_PC16 10 /* 16 bit PC relative reference */ +#define R_MIPS_CALL16 11 /* 16 bit call thru glbl offset tbl */ +#define R_MIPS_CALL R_MIPS_CALL16 +#define R_MIPS_GPREL32 12 + +/* 13, 14, 15 are not defined at this point. */ +#define R_MIPS_UNUSED1 13 +#define R_MIPS_UNUSED2 14 +#define R_MIPS_UNUSED3 15 + +/* + * The remaining relocs are apparently part of the 64-bit Irix ELF ABI. + */ +#define R_MIPS_SHIFT5 16 +#define R_MIPS_SHIFT6 17 + +#define R_MIPS_64 18 +#define R_MIPS_GOT_DISP 19 +#define R_MIPS_GOT_PAGE 20 +#define R_MIPS_GOT_OFST 21 +#define R_MIPS_GOT_HI16 22 +#define R_MIPS_GOT_LO16 23 +#define R_MIPS_SUB 24 +#define R_MIPS_INSERT_A 25 +#define R_MIPS_INSERT_B 26 +#define R_MIPS_DELETE 27 +#define R_MIPS_HIGHER 28 +#define R_MIPS_HIGHEST 29 +#define R_MIPS_CALL_HI16 30 +#define R_MIPS_CALL_LO16 31 +#define R_MIPS_SCN_DISP 32 +#define R_MIPS_REL16 33 +#define R_MIPS_ADD_IMMEDIATE 34 +#define R_MIPS_PJUMP 35 +#define R_MIPS_RELGOT 36 +#define R_MIPS_JALR 37 +/* TLS relocations */ + +#define R_MIPS_TLS_DTPMOD32 38 /* Module number 32 bit */ +#define R_MIPS_TLS_DTPREL32 39 /* Module-relative offset 32 bit */ +#define R_MIPS_TLS_DTPMOD64 40 /* Module number 64 bit */ +#define R_MIPS_TLS_DTPREL64 41 /* Module-relative offset 64 bit */ +#define R_MIPS_TLS_GD 42 /* 16 bit GOT offset for GD */ +#define R_MIPS_TLS_LDM 43 /* 16 bit GOT offset for LDM */ +#define R_MIPS_TLS_DTPREL_HI16 44 /* Module-relative offset, high 16 bits */ +#define R_MIPS_TLS_DTPREL_LO16 45 /* Module-relative offset, low 16 bits */ +#define R_MIPS_TLS_GOTTPREL 46 /* 16 bit GOT offset for IE */ +#define R_MIPS_TLS_TPREL32 47 /* TP-relative offset, 32 bit */ +#define R_MIPS_TLS_TPREL64 48 /* TP-relative offset, 64 bit */ +#define R_MIPS_TLS_TPREL_HI16 49 /* TP-relative offset, high 16 bits */ +#define R_MIPS_TLS_TPREL_LO16 50 /* TP-relative offset, low 16 bits */ + +#define R_MIPS_max 51 + +#define R_TYPE(name) __CONCAT(R_MIPS_,name) + +#define R_MIPS16_min 100 +#define R_MIPS16_26 100 +#define R_MIPS16_GPREL 101 +#define R_MIPS16_GOT16 102 +#define R_MIPS16_CALL16 103 +#define R_MIPS16_HI16 104 +#define R_MIPS16_LO16 105 +#define R_MIPS16_max 106 + + +/* mips dynamic tags */ + +#define DT_MIPS_RLD_VERSION 0x70000001 +#define DT_MIPS_TIME_STAMP 0x70000002 +#define DT_MIPS_ICHECKSUM 0x70000003 +#define DT_MIPS_IVERSION 0x70000004 +#define DT_MIPS_FLAGS 0x70000005 +#define DT_MIPS_BASE_ADDRESS 0x70000006 +#define DT_MIPS_CONFLICT 0x70000008 +#define DT_MIPS_LIBLIST 0x70000009 +#define DT_MIPS_CONFLICTNO 0x7000000b +#define DT_MIPS_LOCAL_GOTNO 0x7000000a /* number of local got ents */ +#define DT_MIPS_LIBLISTNO 0x70000010 +#define DT_MIPS_SYMTABNO 0x70000011 /* number of .dynsym entries */ +#define DT_MIPS_UNREFEXTNO 0x70000012 +#define DT_MIPS_GOTSYM 0x70000013 /* first dynamic sym in got */ +#define DT_MIPS_HIPAGENO 0x70000014 +#define DT_MIPS_RLD_MAP 0x70000016 /* address of loader map */ + +/* + * ELF Flags + */ +#define EF_MIPS_PIC 0x00000002 /* Contains PIC code */ +#define EF_MIPS_CPIC 0x00000004 /* STD PIC calling sequence */ +#define EF_MIPS_ABI2 0x00000020 /* N32 */ + +#define EF_MIPS_ARCH_ASE 0x0f000000 /* Architectural extensions */ +#define EF_MIPS_ARCH_MDMX 0x08000000 /* MDMX multimedia extension */ +#define EF_MIPS_ARCH_M16 0x04000000 /* MIPS-16 ISA extensions */ + +#define EF_MIPS_ARCH 0xf0000000 /* Architecture field */ +#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code */ +#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code */ +#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code */ +#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code */ +#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code */ +#define EF_MIPS_ARCH_32 0x50000000 /* -mips32 code */ +#define EF_MIPS_ARCH_64 0x60000000 /* -mips64 code */ +#define EF_MIPS_ARCH_32R2 0x70000000 /* -mips32r2 code */ +#define EF_MIPS_ARCH_64R2 0x80000000 /* -mips64r2 code */ + +#define EF_MIPS_ABI 0x0000f000 +#define EF_MIPS_ABI_O32 0x00001000 +#define EF_MIPS_ABI_O64 0x00002000 +#define EF_MIPS_ABI_EABI32 0x00003000 +#define EF_MIPS_ABI_EABI64 0x00004000 + +#if defined(__MIPSEB__) +#define ELF32_MACHDEP_ENDIANNESS ELFDATA2MSB +#define ELF64_MACHDEP_ENDIANNESS ELFDATA2MSB +#elif defined(__MIPSEL__) +#define ELF32_MACHDEP_ENDIANNESS ELFDATA2LSB +#define ELF64_MACHDEP_ENDIANNESS ELFDATA2LSB +#elif !defined(HAVE_NBTOOL_CONFIG_H) +#error neither __MIPSEL__ nor __MIPSEB__ are defined. +#endif + +#ifdef _KERNEL +#ifdef _KERNEL_OPT +#include "opt_compat_netbsd.h" +#endif +#ifdef COMPAT_16 +/* + * Up to 1.6, the ELF dynamic loader (ld.elf_so) was not relocatable. + * Tell the kernel ELF exec code not to try relocating the interpreter + * for dynamically-linked ELF binaries. + */ +#define ELF_INTERP_NON_RELOCATABLE +#endif /* COMPAT_16 */ + +/* + * We need to be able to include the ELF header so we can pick out the + * ABI being used. + */ +#ifdef ELFSIZE +#define ELF_MD_PROBE_FUNC ELFNAME2(mips_netbsd,probe) +#define ELF_MD_COREDUMP_SETUP ELFNAME2(coredump,setup) +#endif + +struct exec_package; + +int mips_netbsd_elf32_probe(struct lwp *, struct exec_package *, void *, char *, + vaddr_t *); +void coredump_elf32_setup(struct lwp *, void *); + +int mips_netbsd_elf64_probe(struct lwp *, struct exec_package *, void *, char *, + vaddr_t *); +void coredump_elf64_setup(struct lwp *, void *); +#endif /* _KERNEL */ + +#endif /* _MIPS_ELF_MACHDEP_H_ */ diff --git a/libc/arch-mips64/include/machine/endian.h b/libc/arch-mips64/include/machine/endian.h new file mode 100644 index 0000000..41a9004 --- /dev/null +++ b/libc/arch-mips64/include/machine/endian.h @@ -0,0 +1,70 @@ +/* $OpenBSD: endian.h,v 1.5 2006/02/27 23:35:59 miod Exp $ */ + +/* + * Copyright (c) 2001-2002 Opsycon AB (www.opsycon.se / www.opsycon.com) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#ifndef _MIPS64_ENDIAN_H_ +#define _MIPS64_ENDIAN_H_ + +#ifdef __GNUC__ + +#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2) +#define __swap16md(x) ({ \ + register uint16_t _x = (x); \ + register uint16_t _r; \ + __asm volatile ("wsbh %0, %1" : "=r" (_r) : "r" (_x)); \ + _r; \ +}) + +#define __swap32md(x) ({ \ + register uint32_t _x = (x); \ + register uint32_t _r; \ + __asm volatile ("wsbh %0, %1; rotr %0, %0, 16" : "=r" (_r) : "r" (_x)); \ + _r; \ +}) + +#define __swap64md(x) ({ \ + uint64_t _swap64md_x = (x); \ + (uint64_t) __swap32md(_swap64md_x >> 32) | \ + (uint64_t) __swap32md(_swap64md_x & 0xffffffff) << 32; \ +}) + +/* Tell sys/endian.h we have MD variants of the swap macros. */ +#define MD_SWAP + +#endif /* __mips32r2__ */ +#endif /* __GNUC__ */ + +#if defined(__MIPSEB__) +#define _BYTE_ORDER _BIG_ENDIAN +#else +#define _BYTE_ORDER _LITTLE_ENDIAN +#endif +#define __STRICT_ALIGNMENT +#include <sys/types.h> +#include <sys/endian.h> + +#endif /* _MIPS64_ENDIAN_H_ */ diff --git a/libc/arch-mips64/include/machine/exec.h b/libc/arch-mips64/include/machine/exec.h new file mode 100644 index 0000000..3c63f74 --- /dev/null +++ b/libc/arch-mips64/include/machine/exec.h @@ -0,0 +1,188 @@ +/* $OpenBSD: exec.h,v 1.1 2004/10/18 19:05:36 grange Exp $ */ + +/* + * Copyright (c) 1996-2004 Per Fogelstrom, Opsycon AB + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#ifndef _MIPS64_EXEC_H_ +#define _MIPS64_EXEC_H_ + +#define __LDPGSZ 4096 + +/* + * Define what exec "formats" we should handle. + */ +#define NATIVE_EXEC_ELF +#define NATIVE_ELFSIZE 64 +#define EXEC_SCRIPT + +/* + * If included from sys/exec.h define kernels ELF format. + */ +#ifdef __LP64__ +#define ARCH_ELFSIZE 64 +#define DB_ELFSIZE 64 +#define ELF_TARG_CLASS ELFCLASS64 +#else +#define ARCH_ELFSIZE 32 +#define DB_ELFSIZE 32 +#define ELF_TARG_CLASS ELFCLASS32 +#endif + +#if defined(__MIPSEB__) +#define ELF_TARG_DATA ELFDATA2MSB +#else +#define ELF_TARG_DATA ELFDATA2LSB +#endif +#define ELF_TARG_MACH EM_MIPS + +#define _NLIST_DO_ELF + +#if defined(_LP64) +#define _KERN_DO_ELF64 +#if defined(COMPAT_O32) +#define _KERN_DO_ELF +#endif +#else +#define _KERN_DO_ELF +#endif + +/* Information taken from MIPS ABI supplemental */ + +/* Architecture dependent Segment types - p_type */ +#define PT_MIPS_REGINFO 0x70000000 /* Register usage information */ + +/* Architecture dependent d_tag field for Elf32_Dyn. */ +#define DT_MIPS_RLD_VERSION 0x70000001 /* Runtime Linker Interface ID */ +#define DT_MIPS_TIME_STAMP 0x70000002 /* Timestamp */ +#define DT_MIPS_ICHECKSUM 0x70000003 /* Cksum of ext. str. and com. sizes */ +#define DT_MIPS_IVERSION 0x70000004 /* Version string (string tbl index) */ +#define DT_MIPS_FLAGS 0x70000005 /* Flags */ +#define DT_MIPS_BASE_ADDRESS 0x70000006 /* Segment base address */ +#define DT_MIPS_CONFLICT 0x70000008 /* Adr of .conflict section */ +#define DT_MIPS_LIBLIST 0x70000009 /* Address of .liblist section */ +#define DT_MIPS_LOCAL_GOTNO 0x7000000a /* Number of local .GOT entries */ +#define DT_MIPS_CONFLICTNO 0x7000000b /* Number of .conflict entries */ +#define DT_MIPS_LIBLISTNO 0x70000010 /* Number of .liblist entries */ +#define DT_MIPS_SYMTABNO 0x70000011 /* Number of .dynsym entries */ +#define DT_MIPS_UNREFEXTNO 0x70000012 /* First external DYNSYM */ +#define DT_MIPS_GOTSYM 0x70000013 /* First GOT entry in .dynsym */ +#define DT_MIPS_HIPAGENO 0x70000014 /* Number of GOT page table entries */ +#define DT_MIPS_RLD_MAP 0x70000016 /* Address of debug map pointer */ + +#define DT_PROCNUM (DT_MIPS_RLD_MAP - DT_LOPROC + 1) + +/* + * Legal values for e_flags field of Elf32_Ehdr. + */ +#define EF_MIPS_NOREORDER 0x00000001 /* .noreorder was used */ +#define EF_MIPS_PIC 0x00000002 /* Contains PIC code */ +#define EF_MIPS_CPIC 0x00000004 /* Uses PIC calling sequence */ +#define EF_MIPS_ABI2 0x00000020 /* -n32 on Irix 6 */ +#define EF_MIPS_32BITMODE 0x00000100 /* 64 bit in 32 bit mode... */ +#define EF_MIPS_ARCH 0xf0000000 /* MIPS architecture level */ +#define E_MIPS_ARCH_1 0x00000000 +#define E_MIPS_ARCH_2 0x10000000 +#define E_MIPS_ARCH_3 0x20000000 +#define E_MIPS_ARCH_4 0x30000000 +#define EF_MIPS_ABI 0x0000f000 /* ABI level */ +#define E_MIPS_ABI_NONE 0x00000000 /* ABI level not set */ +#define E_MIPS_ABI_O32 0x00001000 +#define E_MIPS_ABI_O64 0x00002000 +#define E_MIPS_ABI_EABI32 0x00004000 +#define E_MIPS_ABI_EABI64 0x00004000 + +/* + * Mips special sections. + */ +#define SHN_MIPS_ACOMMON 0xff00 /* Allocated common symbols */ +#define SHN_MIPS_SCOMMON 0xff03 /* Small common symbols */ +#define SHN_MIPS_SUNDEFINED 0xff04 /* Small undefined symbols */ + +/* + * Legal values for sh_type field of Elf32_Shdr. + */ +#define SHT_MIPS_LIBLIST 0x70000000 /* Shared objects used in link */ +#define SHT_MIPS_CONFLICT 0x70000002 /* Conflicting symbols */ +#define SHT_MIPS_GPTAB 0x70000003 /* Global data area sizes */ +#define SHT_MIPS_UCODE 0x70000004 /* Reserved for SGI/MIPS compilers */ +#define SHT_MIPS_DEBUG 0x70000005 /* MIPS ECOFF debugging information */ +#define SHT_MIPS_REGINFO 0x70000006 /* Register usage information */ + +/* + * Legal values for sh_flags field of Elf32_Shdr. + */ +#define SHF_MIPS_GPREL 0x10000000 /* Must be part of global data area */ + +#if 0 +/* + * Entries found in sections of type SHT_MIPS_GPTAB. + */ +typedef union { + struct { + Elf32_Word gt_current_g_value; /* -G val used in compilation */ + Elf32_Word gt_unused; /* Not used */ + } gt_header; /* First entry in section */ + struct { + Elf32_Word gt_g_value; /* If this val were used for -G */ + Elf32_Word gt_bytes; /* This many bytes would be used */ + } gt_entry; /* Subsequent entries in section */ +} Elf32_gptab; + +/* + * Entry found in sections of type SHT_MIPS_REGINFO. + */ +typedef struct { + Elf32_Word ri_gprmask; /* General registers used */ + Elf32_Word ri_cprmask[4]; /* Coprocessor registers used */ + Elf32_Sword ri_gp_value; /* $gp register value */ +} Elf32_RegInfo; +#endif + + +/* + * Mips relocations. + */ + +#define R_MIPS_NONE 0 /* No reloc */ +#define R_MIPS_16 1 /* Direct 16 bit */ +#define R_MIPS_32 2 /* Direct 32 bit */ +#define R_MIPS_REL32 3 /* PC relative 32 bit */ +#define R_MIPS_26 4 /* Direct 26 bit shifted */ +#define R_MIPS_HI16 5 /* High 16 bit */ +#define R_MIPS_LO16 6 /* Low 16 bit */ +#define R_MIPS_GPREL16 7 /* GP relative 16 bit */ +#define R_MIPS_LITERAL 8 /* 16 bit literal entry */ +#define R_MIPS_GOT16 9 /* 16 bit GOT entry */ +#define R_MIPS_PC16 10 /* PC relative 16 bit */ +#define R_MIPS_CALL16 11 /* 16 bit GOT entry for function */ +#define R_MIPS_GPREL32 12 /* GP relative 32 bit */ + +#define R_MIPS_64 18 + +#define R_MIPS_REL32_64 ((R_MIPS_64 << 8) | R_MIPS_REL32) + + +#endif /* !_MIPS64_EXEC_H_ */ diff --git a/libc/arch-mips64/include/machine/regdef.h b/libc/arch-mips64/include/machine/regdef.h new file mode 100644 index 0000000..3a7cd68 --- /dev/null +++ b/libc/arch-mips64/include/machine/regdef.h @@ -0,0 +1,99 @@ +/* $OpenBSD: regdef.h,v 1.3 2005/08/07 07:29:44 miod Exp $ */ + +/* + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Ralph Campbell. This file is derived from the MIPS RISC + * Architecture book by Gerry Kane. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)regdef.h 8.1 (Berkeley) 6/10/93 + */ +#ifndef _MIPS_REGDEF_H_ +#define _MIPS_REGDEF_H_ + +#if (_MIPS_SIM == _ABI64) && !defined(__mips_n64) +#define __mips_n64 1 +#endif +#if (_MIPS_SIM == _ABIN32) && !defined(__mips_n32) +#define __mips_n32 1 +#endif + +#define zero $0 /* always zero */ +#define AT $at /* assembler temp */ +#define v0 $2 /* return value */ +#define v1 $3 +#define a0 $4 /* argument registers */ +#define a1 $5 +#define a2 $6 +#define a3 $7 +#if defined(__mips_n32) || defined(__mips_n64) +#define a4 $8 /* expanded register arguments */ +#define a5 $9 +#define a6 $10 +#define a7 $11 +#define ta0 $8 /* alias */ +#define ta1 $9 +#define ta2 $10 +#define ta3 $11 +#define t0 $12 /* temp registers (not saved across subroutine calls) */ +#define t1 $13 +#define t2 $14 +#define t3 $15 +#else +#define t0 $8 /* temp registers (not saved across subroutine calls) */ +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define ta0 $12 /* alias */ +#define ta1 $13 +#define ta2 $14 +#define ta3 $15 +#endif +#define s0 $16 /* saved across subroutine calls (callee saved) */ +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 /* two more temp registers */ +#define t9 $25 +#define k0 $26 /* kernel temporary */ +#define k1 $27 +#define gp $28 /* global pointer */ +#define sp $29 /* stack pointer */ +#define s8 $30 /* one more callee saved */ +#define ra $31 /* return address */ + +#endif /* !_MIPS_REGDEF_H_ */ diff --git a/libc/arch-mips64/include/machine/regnum.h b/libc/arch-mips64/include/machine/regnum.h new file mode 100644 index 0000000..bfe1280 --- /dev/null +++ b/libc/arch-mips64/include/machine/regnum.h @@ -0,0 +1,119 @@ +/* $OpenBSD: regnum.h,v 1.3 2004/08/10 20:28:13 deraadt Exp $ */ + +/* + * Copyright (c) 2001-2002 Opsycon AB (www.opsycon.se / www.opsycon.com) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#ifndef _MIPS64_REGNUM_H_ +#define _MIPS64_REGNUM_H_ + +/* + * Location of the saved registers relative to ZERO. + * Usage is p->p_regs[XX]. + */ +#define ZERO 0 +#define AST 1 +#define V0 2 +#define V1 3 +#define A0 4 +#define A1 5 +#define A2 6 +#define A3 7 +#define T0 8 +#define T1 9 +#define T2 10 +#define T3 11 +#define T4 12 +#define T5 13 +#define T6 14 +#define T7 15 +#define S0 16 +#define S1 17 +#define S2 18 +#define S3 19 +#define S4 20 +#define S5 21 +#define S6 22 +#define S7 23 +#define T8 24 +#define T9 25 +#define K0 26 +#define K1 27 +#define GP 28 +#define SP 29 +#define S8 30 +#define RA 31 +#define SR 32 +#define PS SR /* alias for SR */ +#define MULLO 33 +#define MULHI 34 +#define BADVADDR 35 +#define CAUSE 36 +#define PC 37 +#define IC 38 +#define CPL 39 + +#define NUMSAVEREGS 40 /* Number of registers saved in trap */ + +#define FPBASE NUMSAVEREGS +#define F0 (FPBASE+0) +#define F1 (FPBASE+1) +#define F2 (FPBASE+2) +#define F3 (FPBASE+3) +#define F4 (FPBASE+4) +#define F5 (FPBASE+5) +#define F6 (FPBASE+6) +#define F7 (FPBASE+7) +#define F8 (FPBASE+8) +#define F9 (FPBASE+9) +#define F10 (FPBASE+10) +#define F11 (FPBASE+11) +#define F12 (FPBASE+12) +#define F13 (FPBASE+13) +#define F14 (FPBASE+14) +#define F15 (FPBASE+15) +#define F16 (FPBASE+16) +#define F17 (FPBASE+17) +#define F18 (FPBASE+18) +#define F19 (FPBASE+19) +#define F20 (FPBASE+20) +#define F21 (FPBASE+21) +#define F22 (FPBASE+22) +#define F23 (FPBASE+23) +#define F24 (FPBASE+24) +#define F25 (FPBASE+25) +#define F26 (FPBASE+26) +#define F27 (FPBASE+27) +#define F28 (FPBASE+28) +#define F29 (FPBASE+29) +#define F30 (FPBASE+30) +#define F31 (FPBASE+31) +#define FSR (FPBASE+32) + +#define NUMFPREGS 33 + +#define NREGS (NUMSAVEREGS + NUMFPREGS) + +#endif /* !_MIPS64_REGNUM_H_ */ diff --git a/libc/arch-mips64/include/machine/setjmp.h b/libc/arch-mips64/include/machine/setjmp.h new file mode 100644 index 0000000..55ba7be --- /dev/null +++ b/libc/arch-mips64/include/machine/setjmp.h @@ -0,0 +1,10 @@ +/* $OpenBSD: setjmp.h,v 1.2 2004/08/10 21:10:56 pefo Exp $ */ + +/* Public domain */ + +#ifndef _MIPS_SETJMP_H_ +#define _MIPS_SETJMP_H_ + +#define _JBLEN 157 /* size, in longs, of a jmp_buf */ + +#endif /* !_MIPS_SETJMP_H_ */ diff --git a/libc/arch-mips64/include/machine/signal.h b/libc/arch-mips64/include/machine/signal.h new file mode 100644 index 0000000..b31715c --- /dev/null +++ b/libc/arch-mips64/include/machine/signal.h @@ -0,0 +1,51 @@ +/* $OpenBSD: signal.h,v 1.8 2006/01/09 18:18:37 millert Exp $ */ + +/* + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Ralph Campbell. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)signal.h 8.1 (Berkeley) 6/10/93 + */ + +#ifndef _MIPS_SIGNAL_H_ +#define _MIPS_SIGNAL_H_ + +#define SC_REGMASK (0*REGSZ) +#define SC_STATUS (1*REGSZ) +#define SC_PC (2*REGSZ) +#define SC_REGS (SC_PC+8) +#define SC_FPREGS (SC_REGS+32*8) +#define SC_ACX (SC_FPREGS+32*REGSZ_FP) +#define SC_USED_MATH (SC_ACX+3*REGSZ) +/* OpenBSD compatibility */ +#define SC_MASK SC_REGMASK +#define SC_FPUSED SC_USED_MATH + +#endif /* !_MIPS_SIGNAL_H_ */ diff --git a/libc/arch-mips64/mips64.mk b/libc/arch-mips64/mips64.mk new file mode 100644 index 0000000..230cb26 --- /dev/null +++ b/libc/arch-mips64/mips64.mk @@ -0,0 +1,72 @@ +# mips64 specific configs + +libc_common_src_files_mips64 := \ + bionic/memchr.c \ + bionic/memcmp.c \ + bionic/memmove.c \ + bionic/memrchr.c \ + bionic/strchr.cpp \ + bionic/strnlen.c \ + bionic/strrchr.cpp \ + upstream-freebsd/lib/libc/string/wcscat.c \ + upstream-freebsd/lib/libc/string/wcschr.c \ + upstream-freebsd/lib/libc/string/wcscmp.c \ + upstream-freebsd/lib/libc/string/wcscpy.c \ + upstream-freebsd/lib/libc/string/wcslen.c \ + upstream-freebsd/lib/libc/string/wcsrchr.c \ + upstream-freebsd/lib/libc/string/wmemcmp.c \ + upstream-freebsd/lib/libc/string/wmemmove.c \ + upstream-openbsd/lib/libc/string/stpcpy.c \ + upstream-openbsd/lib/libc/string/stpncpy.c \ + upstream-openbsd/lib/libc/string/strcat.c \ + upstream-openbsd/lib/libc/string/strcmp.c \ + upstream-openbsd/lib/libc/string/strcpy.c \ + upstream-openbsd/lib/libc/string/strlcat.c \ + upstream-openbsd/lib/libc/string/strlcpy.c \ + upstream-openbsd/lib/libc/string/strlen.c \ + upstream-openbsd/lib/libc/string/strncat.c \ + upstream-openbsd/lib/libc/string/strncmp.c \ + upstream-openbsd/lib/libc/string/strncpy.c \ + +# Fortify implementations of libc functions. +libc_common_src_files_mips64 += \ + bionic/__memcpy_chk.cpp \ + bionic/__memset_chk.cpp \ + bionic/__strcpy_chk.cpp \ + bionic/__strcat_chk.cpp \ + + +########################################## +### CPU specific source files +libc_bionic_src_files_mips64 := \ + arch-mips64/bionic/__bionic_clone.S \ + arch-mips64/bionic/_exit_with_stack_teardown.S \ + arch-mips64/bionic/__get_sp.S \ + arch-mips64/bionic/_setjmp.S \ + arch-mips64/bionic/setjmp.S \ + arch-mips64/bionic/sigsetjmp.S \ + arch-mips64/bionic/syscall.S \ + arch-mips64/bionic/vfork.S \ + +# FIXME TODO +## libc_bionic_src_files_mips64 += arch-mips64/string/memcpy.S +## libc_bionic_src_files_mips64 += arch-mips64/string/memset.S +libc_bionic_src_files_mips64 += bionic/memcpy.cpp +libc_bionic_src_files_mips64 += bionic/memset.c + + +libc_crt_target_cflags_mips64 := \ + $($(my_2nd_arch_prefix)TARGET_GLOBAL_CFLAGS) \ + -I$(LOCAL_PATH)/arch-mips64/include + +libc_crt_target_crtbegin_file_mips64 := \ + $(LOCAL_PATH)/arch-mips64/bionic/crtbegin.c + +libc_crt_target_crtbegin_so_file_mips64 := \ + $(LOCAL_PATH)/arch-common/bionic/crtbegin_so.c + +libc_crt_target_so_cflags_mips64 := \ + -fPIC + +libc_crt_target_ldflags_mips64 := \ + -melf64ltsmip diff --git a/libc/arch-mips64/string/memcpy.S b/libc/arch-mips64/string/memcpy.S new file mode 100644 index 0000000..dc91096 --- /dev/null +++ b/libc/arch-mips64/string/memcpy.S @@ -0,0 +1,423 @@ +/* + * Copyright (c) 2009 + * MIPS Technologies, Inc., California. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the MIPS Technologies, Inc., nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE MIPS TECHNOLOGIES, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE MIPS TECHNOLOGIES, INC. BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/************************************************************************ + * + * memcpy.S + * Version: "043009" + * + ************************************************************************/ + + +/************************************************************************ + * Include files + ************************************************************************/ + +#include <private/bionic_asm.h> + + +/* + * This routine could be optimized for MIPS64. The current code only + * uses MIPS32 instructions. + */ +#if defined(__MIPSEB__) +# define LWHI lwl /* high part is left in big-endian */ +# define SWHI swl /* high part is left in big-endian */ +# define LWLO lwr /* low part is right in big-endian */ +# define SWLO swr /* low part is right in big-endian */ +#endif + +#if defined(__MIPSEL__) +# define LWHI lwr /* high part is right in little-endian */ +# define SWHI swr /* high part is right in little-endian */ +# define LWLO lwl /* low part is left in big-endian */ +# define SWLO swl /* low part is left in big-endian */ +#endif + +LEAF(memcpy,0) + + .set noreorder + .set noat +/* + * Below we handle the case where memcpy is called with overlapping src and dst. + * Although memcpy is not required to handle this case, some parts of Android like Skia + * rely on such usage. We call memmove to handle such cases. + */ + subu t0,a0,a1 + sra AT,t0,31 + xor t1,t0,AT + subu t0,t1,AT + sltu AT,t0,a2 + beq AT,zero,.Lmemcpy + la t9,memmove + jr t9 + nop +.Lmemcpy: + slti AT,a2,8 + bne AT,zero,.Llast8 + move v0,a0 # memcpy returns the dst pointer + +# Test if the src and dst are word-aligned, or can be made word-aligned + xor t8,a1,a0 + andi t8,t8,0x3 # t8 is a0/a1 word-displacement + + bne t8,zero,.Lunaligned + negu a3,a0 + + andi a3,a3,0x3 # we need to copy a3 bytes to make a0/a1 aligned + beq a3,zero,.Lchk16w # when a3=0 then the dst (a0) is word-aligned + subu a2,a2,a3 # now a2 is the remining bytes count + + LWHI t8,0(a1) + addu a1,a1,a3 + SWHI t8,0(a0) + addu a0,a0,a3 + +# Now the dst/src are mutually word-aligned with word-aligned addresses +.Lchk16w: + andi t8,a2,0x3f # any whole 64-byte chunks? + # t8 is the byte count after 64-byte chunks + + beq a2,t8,.Lchk8w # if a2==t8, no 64-byte chunks + # There will be at most 1 32-byte chunk after it + subu a3,a2,t8 # subtract from a2 the reminder + # Here a3 counts bytes in 16w chunks + addu a3,a0,a3 # Now a3 is the final dst after 64-byte chunks + + addu t0,a0,a2 # t0 is the "past the end" address + +# When in the loop we exercise "pref 30,x(a0)", the a0+x should not be past +# the "t0-32" address +# This means: for x=128 the last "safe" a0 address is "t0-160" +# Alternatively, for x=64 the last "safe" a0 address is "t0-96" +# In the current version we will use "pref 30,128(a0)", so "t0-160" is the limit + subu t9,t0,160 # t9 is the "last safe pref 30,128(a0)" address + + pref 0,0(a1) # bring the first line of src, addr 0 + pref 0,32(a1) # bring the second line of src, addr 32 + pref 0,64(a1) # bring the third line of src, addr 64 + pref 30,32(a0) # safe, as we have at least 64 bytes ahead +# In case the a0 > t9 don't use "pref 30" at all + sgtu v1,a0,t9 + bgtz v1,.Lloop16w # skip "pref 30,64(a0)" for too short arrays + nop +# otherwise, start with using pref30 + pref 30,64(a0) +.Lloop16w: + pref 0,96(a1) + lw t0,0(a1) + bgtz v1,.Lskip_pref30_96 # skip "pref 30,96(a0)" + lw t1,4(a1) + pref 30,96(a0) # continue setting up the dest, addr 96 +.Lskip_pref30_96: + lw t2,8(a1) + lw t3,12(a1) + lw t4,16(a1) + lw t5,20(a1) + lw t6,24(a1) + lw t7,28(a1) + pref 0,128(a1) # bring the next lines of src, addr 128 + + sw t0,0(a0) + sw t1,4(a0) + sw t2,8(a0) + sw t3,12(a0) + sw t4,16(a0) + sw t5,20(a0) + sw t6,24(a0) + sw t7,28(a0) + + lw t0,32(a1) + bgtz v1,.Lskip_pref30_128 # skip "pref 30,128(a0)" + lw t1,36(a1) + pref 30,128(a0) # continue setting up the dest, addr 128 +.Lskip_pref30_128: + lw t2,40(a1) + lw t3,44(a1) + lw t4,48(a1) + lw t5,52(a1) + lw t6,56(a1) + lw t7,60(a1) + pref 0, 160(a1) # bring the next lines of src, addr 160 + + sw t0,32(a0) + sw t1,36(a0) + sw t2,40(a0) + sw t3,44(a0) + sw t4,48(a0) + sw t5,52(a0) + sw t6,56(a0) + sw t7,60(a0) + + addiu a0,a0,64 # adding 64 to dest + sgtu v1,a0,t9 + bne a0,a3,.Lloop16w + addiu a1,a1,64 # adding 64 to src + move a2,t8 + +# Here we have src and dest word-aligned but less than 64-bytes to go + +.Lchk8w: + pref 0, 0x0(a1) + andi t8,a2,0x1f # is there a 32-byte chunk? + # the t8 is the reminder count past 32-bytes + beq a2,t8,.Lchk1w # when a2=t8, no 32-byte chunk + nop + + lw t0,0(a1) + lw t1,4(a1) + lw t2,8(a1) + lw t3,12(a1) + lw t4,16(a1) + lw t5,20(a1) + lw t6,24(a1) + lw t7,28(a1) + addiu a1,a1,32 + + sw t0,0(a0) + sw t1,4(a0) + sw t2,8(a0) + sw t3,12(a0) + sw t4,16(a0) + sw t5,20(a0) + sw t6,24(a0) + sw t7,28(a0) + addiu a0,a0,32 + +.Lchk1w: + andi a2,t8,0x3 # now a2 is the reminder past 1w chunks + beq a2,t8,.Llast8 + subu a3,t8,a2 # a3 is count of bytes in 1w chunks + addu a3,a0,a3 # now a3 is the dst address past the 1w chunks + +# copying in words (4-byte chunks) +.LwordCopy_loop: + lw t3,0(a1) # the first t3 may be equal t0 ... optimize? + addiu a1,a1,4 + addiu a0,a0,4 + bne a0,a3,.LwordCopy_loop + sw t3,-4(a0) + +# For the last (<8) bytes +.Llast8: + blez a2,.Lleave + addu a3,a0,a2 # a3 is the last dst address +.Llast8loop: + lb v1,0(a1) + addiu a1,a1,1 + addiu a0,a0,1 + bne a0,a3,.Llast8loop + sb v1,-1(a0) + +.Lleave: + j ra + nop + +# +# UNALIGNED case +# + +.Lunaligned: + # got here with a3="negu a0" + andi a3,a3,0x3 # test if the a0 is word aligned + beqz a3,.Lua_chk16w + subu a2,a2,a3 # bytes left after initial a3 bytes + + LWHI v1,0(a1) + LWLO v1,3(a1) + addu a1,a1,a3 # a3 may be here 1, 2 or 3 + SWHI v1,0(a0) + addu a0,a0,a3 # below the dst will be word aligned (NOTE1) + +.Lua_chk16w: + andi t8,a2,0x3f # any whole 64-byte chunks? + # t8 is the byte count after 64-byte chunks + beq a2,t8,.Lua_chk8w # if a2==t8, no 64-byte chunks + # There will be at most 1 32-byte chunk after it + subu a3,a2,t8 # subtract from a2 the reminder + # Here a3 counts bytes in 16w chunks + addu a3,a0,a3 # Now a3 is the final dst after 64-byte chunks + + addu t0,a0,a2 # t0 is the "past the end" address + + subu t9,t0,160 # t9 is the "last safe pref 30,128(a0)" address + + pref 0,0(a1) # bring the first line of src, addr 0 + pref 0,32(a1) # bring the second line of src, addr 32 + pref 0,64(a1) # bring the third line of src, addr 64 + pref 30,32(a0) # safe, as we have at least 64 bytes ahead +# In case the a0 > t9 don't use "pref 30" at all + sgtu v1,a0,t9 + bgtz v1,.Lua_loop16w # skip "pref 30,64(a0)" for too short arrays + nop +# otherwise, start with using pref30 + pref 30,64(a0) +.Lua_loop16w: + pref 0,96(a1) + LWHI t0,0(a1) + LWLO t0,3(a1) + LWHI t1,4(a1) + bgtz v1,.Lua_skip_pref30_96 + LWLO t1,7(a1) + pref 30,96(a0) # continue setting up the dest, addr 96 +.Lua_skip_pref30_96: + LWHI t2,8(a1) + LWLO t2,11(a1) + LWHI t3,12(a1) + LWLO t3,15(a1) + LWHI t4,16(a1) + LWLO t4,19(a1) + LWHI t5,20(a1) + LWLO t5,23(a1) + LWHI t6,24(a1) + LWLO t6,27(a1) + LWHI t7,28(a1) + LWLO t7,31(a1) + pref 0,128(a1) # bring the next lines of src, addr 128 + + sw t0,0(a0) + sw t1,4(a0) + sw t2,8(a0) + sw t3,12(a0) + sw t4,16(a0) + sw t5,20(a0) + sw t6,24(a0) + sw t7,28(a0) + + LWHI t0,32(a1) + LWLO t0,35(a1) + LWHI t1,36(a1) + bgtz v1,.Lua_skip_pref30_128 + LWLO t1,39(a1) + pref 30,128(a0) # continue setting up the dest, addr 128 +.Lua_skip_pref30_128: + LWHI t2,40(a1) + LWLO t2,43(a1) + LWHI t3,44(a1) + LWLO t3,47(a1) + LWHI t4,48(a1) + LWLO t4,51(a1) + LWHI t5,52(a1) + LWLO t5,55(a1) + LWHI t6,56(a1) + LWLO t6,59(a1) + LWHI t7,60(a1) + LWLO t7,63(a1) + pref 0, 160(a1) # bring the next lines of src, addr 160 + + sw t0,32(a0) + sw t1,36(a0) + sw t2,40(a0) + sw t3,44(a0) + sw t4,48(a0) + sw t5,52(a0) + sw t6,56(a0) + sw t7,60(a0) + + addiu a0,a0,64 # adding 64 to dest + sgtu v1,a0,t9 + bne a0,a3,.Lua_loop16w + addiu a1,a1,64 # adding 64 to src + move a2,t8 + +# Here we have src and dest word-aligned but less than 64-bytes to go + +.Lua_chk8w: + pref 0, 0x0(a1) + andi t8,a2,0x1f # is there a 32-byte chunk? + # the t8 is the reminder count + beq a2,t8,.Lua_chk1w # when a2=t8, no 32-byte chunk + nop + + LWHI t0,0(a1) + LWLO t0,3(a1) + LWHI t1,4(a1) + LWLO t1,7(a1) + LWHI t2,8(a1) + LWLO t2,11(a1) + LWHI t3,12(a1) + LWLO t3,15(a1) + LWHI t4,16(a1) + LWLO t4,19(a1) + LWHI t5,20(a1) + LWLO t5,23(a1) + LWHI t6,24(a1) + LWLO t6,27(a1) + LWHI t7,28(a1) + LWLO t7,31(a1) + addiu a1,a1,32 + + sw t0,0(a0) + sw t1,4(a0) + sw t2,8(a0) + sw t3,12(a0) + sw t4,16(a0) + sw t5,20(a0) + sw t6,24(a0) + sw t7,28(a0) + addiu a0,a0,32 + +.Lua_chk1w: + andi a2,t8,0x3 # now a2 is the reminder past 1w chunks + beq a2,t8,.Lua_smallCopy + subu a3,t8,a2 # a3 is count of bytes in 1w chunks + addu a3,a0,a3 # now a3 is the dst address past the 1w chunks + +# copying in words (4-byte chunks) +.Lua_wordCopy_loop: + LWHI v1,0(a1) + LWLO v1,3(a1) + addiu a1,a1,4 + addiu a0,a0,4 # note: dst=a0 is word aligned here, see NOTE1 + bne a0,a3,.Lua_wordCopy_loop + sw v1,-4(a0) + +# Now less than 4 bytes (value in a2) left to copy +.Lua_smallCopy: + beqz a2,.Lleave + addu a3,a0,a2 # a3 is the last dst address +.Lua_smallCopy_loop: + lb v1,0(a1) + addiu a1,a1,1 + addiu a0,a0,1 + bne a0,a3,.Lua_smallCopy_loop + sb v1,-1(a0) + + j ra + nop + + .set at + .set reorder + +END(memcpy) + + +/************************************************************************ + * Implementation : Static functions + ************************************************************************/ diff --git a/libc/arch-mips64/string/memset.S b/libc/arch-mips64/string/memset.S new file mode 100644 index 0000000..3e630ca --- /dev/null +++ b/libc/arch-mips64/string/memset.S @@ -0,0 +1,322 @@ +/* + * Copyright (c) 2009 + * MIPS Technologies, Inc., California. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the MIPS Technologies, Inc., nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE MIPS TECHNOLOGIES, INC. ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE MIPS TECHNOLOGIES, INC. BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/************************************************************************ + * + * memset.S, version "64h" with 1 cache line horizon for "pref 30" and 14 nops + * Version: "043009" + * + ************************************************************************/ + + +/************************************************************************ + * Include files + ************************************************************************/ + +#include <private/bionic_asm.h> + +/* + * This routine could be optimized for MIPS64. The current code only + * uses MIPS32 instructions. + */ + +#if defined(__MIPSEB__) +# define SWHI swl /* high part is left in big-endian */ +# define SWLO swr /* low part is right in big-endian */ +#endif + +#if defined(__MIPSEL__) +# define SWHI swr /* high part is right in little-endian */ +# define SWLO swl /* low part is left in little-endian */ +#endif + +#if !(defined(XGPROF) || defined(XPROF)) +#undef SETUP_GP +#define SETUP_GP +#endif + +#ifdef NDEBUG +#define DBG # +#else +#define DBG +#endif + +/* + * void _memset16(uint16_t* dst, uint16_t value, size_t size); + */ + +LEAF(_memset16,0) + .set noreorder +DBG /* Check parameters */ +DBG andi t0,a0,1 # a0 must be halfword aligned +DBG tne t0,zero +DBG andi t2,a2,1 # a2 must be even +DBG tne t2,zero + +#ifdef FIXARGS + # ensure count is even +#if (__mips==32) && (__mips_isa_rev>=2) + ins a2,zero,0,1 +#else + ori a2,1 + xori a2,1 +#endif +#endif + +#if (__mips==32) && (__mips_isa_rev>=2) + ins a1,a1,16,16 +#else + andi a1,0xffff + sll t3,a1,16 + or a1,t3 +#endif + + beqz a2,.Ldone + andi t1,a0,2 + beqz t1,.Lalignok + addu t0,a0,a2 # t0 is the "past the end" address + sh a1,0(a0) # store one halfword to get aligned + addu a0,2 + subu a2,2 +.Lalignok: + slti t1,a2,4 # .Laligned for 4 or more bytes + beqz t1,.Laligned + sne t1,a2,2 # one more halfword? + bnez t1,.Ldone + nop + sh a1,0(a0) +.Ldone: + j ra + nop + .set reorder +END(_memset16) + +/* + * void _memset32(uint32_t* dst, uint32_t value, size_t size); + */ + +LEAF(_memset32,0) + .set noreorder +DBG /* Check parameters */ +DBG andi t0,a0,3 # a0 must be word aligned +DBG tne t0,zero +DBG andi t2,a2,3 # a2 must be a multiple of 4 bytes +DBG tne t2,zero + +#ifdef FIXARGS + # ensure count is a multiple of 4 +#if (__mips==32) && (__mips_isa_rev>=2) + ins $a2,$0,0,2 +#else + ori a2,3 + xori a2,3 +#endif +#endif + + bnez a2,.Laligned # any work to do? + addu t0,a0,a2 # t0 is the "past the end" address + + j ra + nop + .set reorder +END(_memset32) + +LEAF(memset,0) + + .set noreorder + .set noat + + addu t0,a0,a2 # t0 is the "past the end" address + slti AT,a2,4 # is a2 less than 4? + bne AT,zero,.Llast4 # if yes, go to last4 + move v0,a0 # memset returns the dst pointer + + beq a1,zero,.Lset0 + subu v1,zero,a0 + + # smear byte into 32 bit word +#if (__mips==32) && (__mips_isa_rev>=2) + ins a1, a1, 8, 8 # Replicate fill byte into half-word. + ins a1, a1, 16, 16 # Replicate fill byte into word. +#else + and a1,0xff + sll AT,a1,8 + or a1,AT + sll AT,a1,16 + or a1,AT +#endif + +.Lset0: + andi v1,v1,0x3 # word-unaligned address? + beq v1,zero,.Laligned # v1 is the unalignment count + subu a2,a2,v1 + SWHI a1,0(a0) + addu a0,a0,v1 + +# Here we have the "word-aligned" a0 (until the "last4") +.Laligned: + andi t8,a2,0x3f # any 64-byte chunks? + # t8 is the byte count past 64-byte chunks + beq a2,t8,.Lchk8w # when a2==t8, no 64-byte chunks + # There will be at most 1 32-byte chunk then + subu a3,a2,t8 # subtract from a2 the reminder + # Here a3 counts bytes in 16w chunks + addu a3,a0,a3 # Now a3 is the final dst after 64-byte chunks + +# Find out, if there are any 64-byte chunks after which will be still at least +# 96 bytes left. The value "96" is calculated as needed buffer for +# "pref 30,64(a0)" prefetch, which can be used as "pref 30,0(a0)" after +# incrementing "a0" by 64. +# For "a2" below 160 there will be no such "pref 30 safe" 64-byte chunk. +# + sltiu v1,a2,160 + bgtz v1,.Lloop16w_nopref30 # skip "pref 30,0(a0)" + subu t7,a2,96 # subtract "pref 30 unsafe" region + # below we have at least 1 64-byte chunk which is "pref 30 safe" + andi t6,t7,0x3f # t6 is past "64-byte safe chunks" reminder + subu t5,t7,t6 # subtract from t7 the reminder + # Here t5 counts bytes in 16w "safe" chunks + addu t4,a0,t5 # Now t4 is the dst after 64-byte "safe" chunks + +# Don't use "pref 30,0(a0)" for a0 in a "middle" of a cache line +# pref 30,0(a0) +# Here we are in the region, where it is safe to use "pref 30,64(a0)" +.Lloop16w: + addiu a0,a0,64 + pref 30,-32(a0) # continue setting up the dest, addr 64-32 + sw a1,-64(a0) + sw a1,-60(a0) + sw a1,-56(a0) + sw a1,-52(a0) + sw a1,-48(a0) + sw a1,-44(a0) + sw a1,-40(a0) + sw a1,-36(a0) + nop + nop # the extra nop instructions help to balance + nop # cycles needed for "store" + "fill" + "evict" + nop # For 64byte store there are needed 8 fill + nop # and 8 evict cycles, i.e. at least 32 instr. + nop + nop + pref 30,0(a0) # continue setting up the dest, addr 64-0 + sw a1,-32(a0) + sw a1,-28(a0) + sw a1,-24(a0) + sw a1,-20(a0) + sw a1,-16(a0) + sw a1,-12(a0) + sw a1,-8(a0) + sw a1,-4(a0) + nop + nop + nop + nop # NOTE: adding 14 nop-s instead of 12 nop-s + nop # gives better results for "fast" memory + nop + bne a0,t4,.Lloop16w + nop + + beq a0,a3,.Lchk8w # maybe no more 64-byte chunks? + nop # this "delayed slot" is useless ... + +.Lloop16w_nopref30: # there could be up to 3 "64-byte nopref30" chunks + addiu a0,a0,64 + sw a1,-64(a0) + sw a1,-60(a0) + sw a1,-56(a0) + sw a1,-52(a0) + sw a1,-48(a0) + sw a1,-44(a0) + sw a1,-40(a0) + sw a1,-36(a0) + sw a1,-32(a0) + sw a1,-28(a0) + sw a1,-24(a0) + sw a1,-20(a0) + sw a1,-16(a0) + sw a1,-12(a0) + sw a1,-8(a0) + bne a0,a3,.Lloop16w_nopref30 + sw a1,-4(a0) + +.Lchk8w: # t8 here is the byte count past 64-byte chunks + + andi t7,t8,0x1f # is there a 32-byte chunk? + # the t7 is the reminder count past 32-bytes + beq t8,t7,.Lchk1w # when t8==t7, no 32-byte chunk + move a2,t7 + + sw a1,0(a0) + sw a1,4(a0) + sw a1,8(a0) + sw a1,12(a0) + sw a1,16(a0) + sw a1,20(a0) + sw a1,24(a0) + sw a1,28(a0) + addiu a0,a0,32 + +.Lchk1w: + andi t8,a2,0x3 # now t8 is the reminder past 1w chunks + beq a2,t8,.Llast4aligned + subu a3,a2,t8 # a3 is the count of bytes in 1w chunks + addu a3,a0,a3 # now a3 is the dst address past the 1w chunks + +# copying in words (4-byte chunks) +.LwordCopy_loop: + addiu a0,a0,4 + bne a0,a3,.LwordCopy_loop + sw a1,-4(a0) + +# store last 0-3 bytes +# this will repeat the last store if the memset finishes on a word boundary +.Llast4aligned: + j ra + SWLO a1,-1(t0) + +.Llast4: + beq a0,t0,.Llast4e +.Llast4l: + addiu a0,a0,1 + bne a0,t0,.Llast4l + sb a1,-1(a0) +.Llast4e: + j ra + nop + + .set at + .set reorder + +END(memset) + + +/************************************************************************ + * Implementation : Static functions + ************************************************************************/ diff --git a/libc/arch-mips64/string/mips-string-ops.h b/libc/arch-mips64/string/mips-string-ops.h new file mode 100644 index 0000000..e635ba1 --- /dev/null +++ b/libc/arch-mips64/string/mips-string-ops.h @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2010 MIPS Technologies, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer + * in the documentation and/or other materials provided with + * the distribution. + * * Neither the name of MIPS Technologies Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __MIPS_STRING_OPS_H +#define __MIPS_STRING_OPS_H + /* This definition of the byte bitfields uses the + assumption that the layout of the bitfields is + equivalent to the layout in memory. Generally, + for the MIPS ABIs, this is true. If you compile + the strcmp.c file with -DSMOKE_TEST_NEW_STRCMP, + this assumption will be tested. + + Also, regardless of char signedness, ANSI C dictates that + strcmp() treats each character as unsigned char. For + strlen and the like, signedness doesn't matter. + + Also, this code assumes that there are 8-bits per 'char'. */ + +#if __mips64 +typedef struct bits +{ + unsigned long B0:8, B1:8, B2:8, B3:8, B4:8, B5:8, B6:8, B7:8; +} bits_t; +#else +typedef struct bits +{ + unsigned long B0:8, B1:8, B2:8, B3:8; +} bits_t; +#endif + +#ifndef _ULW + /* for MIPS GCC, there is no unaligned builtins - so this code forces + the compiler to treat the pointer access as unaligned. */ +struct ulw +{ + unsigned long b; +} __attribute__ ((packed)); + +#define _ULW(__x) ((struct ulw *) ((char *)(&__x)))->b; +#endif + +/* This union assumes that small structures can be in registers. If + not, then memory accesses will be done - not optimal, but ok. */ +typedef union +{ + unsigned long v; + bits_t b; +} bitfields_t; + +#ifndef detect_zero +/* __mips_dsp, __mips_dspr2, and __mips64 are predefined by + the compiler, based on command line options. */ +#if (__mips_dsp || __mips_dspr2) && !__mips64 +#define __mips_using_dsp 1 + +/* DSP 4-lane (8 unsigned bits per line) subtract and saturate + * Intrinsic operation. How this works: + * Given a 4-byte string of "ABC\0", subtract this as + * an unsigned integer from 0x01010101: + * 0x01010101 + * - 0x41424300 + * ----------- + ( 0xbfbebe01 <-- answer without saturation + * 0x00000001 <-- answer with saturation + * When this 4-lane vector is treated as an unsigned int value, + * a non-zero answer indicates the presence of a zero in the + * original 4-byte argument. */ + +typedef signed char v4i8 __attribute__ ((vector_size (4))); + +#define detect_zero(__x,__y,__01s,__80s)\ + ((unsigned) __builtin_mips_subu_s_qb((v4i8) __01s,(v4i8) __x)) + + /* sets all 4 lanes to requested byte. */ +#define set_byte_lanes(__x) ((unsigned) __builtin_mips_repl_qb(__x)) + + /* sets all 4 lanes to 0x01. */ +#define def_and_set_01(__x) unsigned long __x = (unsigned) __builtin_mips_repl_qb(0x01) + + /* sets all 4 lanes to 0x80. Not needed when subu_s.qb used. */ +#define def_and_set_80(__x) /* do nothing */ + +#else + /* this version, originally published in the 80's, uses + a reverse-carry-set like determination of the zero byte. + The steps are, for __x = 0x31ff0001: + __x - _01s = 0x30fdff00 + ~__x = 0xce00fffe + ((__x - _01s) & ~__x) = 0x0000ff00 + x & _80s = 0x00008000 <- byte 3 was zero + Some implementaions naively assume that characters are + always 7-bit unsigned ASCII. With that assumption, the + "& ~x" is usually discarded. Since character strings + are 8-bit, the and is needed to catch the case of + a false positive when the byte is 0x80. */ + +#define detect_zero(__x,__y,_01s,_80s)\ + ((unsigned) (((__x) - _01s) & ~(__x)) & _80s) + +#if __mips64 +#define def_and_set_80(__x) unsigned long __x = 0x8080808080808080ul +#define def_and_set_01(__x) unsigned long __x = 0x0101010101010101ul +#else +#define def_and_set_80(__x) unsigned long __x = 0x80808080ul +#define def_and_set_01(__x) unsigned long __x = 0x01010101ul +#endif + +#endif +#endif + +/* dealing with 'void *' conversions without using extra variables. */ +#define get_byte(__x,__idx) (((unsigned char *) (__x))[__idx]) +#define set_byte(__x,__idx,__fill) ((unsigned char *) (__x))[__idx] = (__fill) +#define get_word(__x,__idx) (((unsigned long *) (__x))[__idx]) +#define set_word(__x,__idx,__fill) ((unsigned long *) (__x))[__idx] = (__fill) +#define inc_ptr_as(__type,__x,__inc) __x = (void *) (((__type) __x) + (__inc)) +#define cvt_ptr_to(__type,__x) ((__type) (__x)) + +#endif diff --git a/libc/arch-mips64/string/mips_strlen.c b/libc/arch-mips64/string/mips_strlen.c new file mode 100644 index 0000000..37e5865 --- /dev/null +++ b/libc/arch-mips64/string/mips_strlen.c @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2010 MIPS Technologies, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer + * in the documentation and/or other materials provided with + * the distribution. + * * Neither the name of MIPS Technologies Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <string.h> +#include "mips-string-ops.h" + +#define do_strlen_word(__av) {\ + if (detect_zero(x,x,_01s,_80s)) break;\ + x = __av;\ + cnt += sizeof (unsigned);\ + } + +#define do_strlen_byte(__x) {\ + if ((bx.b.B##__x) == 0) break;\ + ++cnt;\ + } + +#if SMOKE_TEST_MIPS_STRLEN +#define strlen my_strlen +#endif + +size_t +strlen (const char *_a) +{ + int cnt = 0; + unsigned long x; + + /* align the string to word boundary so we can do word at a time. */ + if ((cvt_ptr_to (unsigned long, _a) & (sizeof (unsigned long) - 1)) != 0) + { + if ((cvt_ptr_to (unsigned long, _a) & 1) != 0) + { + if (get_byte (_a, 0) == 0) + return cnt; + /* set bit 1 so 2-bytes are checked and incremented. */ + inc_ptr_as (char *, _a, 1); + ++cnt; + } + if ((cvt_ptr_to (unsigned long, _a) & 2) != 0) + { + if (get_byte (_a, 0) == 0) + return cnt + 0; + if (get_byte (_a, 1) == 0) + return cnt + 1; + inc_ptr_as (char *, _a, 2); + cnt += 2; + } + } + +#if __mips64 +#error strlen: mips64 check for 4-byte alignment not implemented. +#endif + + if (1) + { + def_and_set_01 (_01s); + def_and_set_80 (_80s); + + /* as advantagous as it is to performance, this code cannot pre-load + the following word, nor can it prefetch the next line at the start + of the loop since the string can be at the end of a page with the + following page unmapped. There are tests in the suite to catch + any attempt to go beyond the current word. */ + x = get_word (_a, 0); + while (1) + { + /* doing 8 words should cover most strings. */ + do_strlen_word (get_word (_a, 1)); + do_strlen_word (get_word (_a, 2)); + do_strlen_word (get_word (_a, 3)); + do_strlen_word (get_word (_a, 4)); + do_strlen_word (get_word (_a, 5)); + do_strlen_word (get_word (_a, 6)); + do_strlen_word (get_word (_a, 7)); + do_strlen_word (get_word (_a, 8)); + inc_ptr_as (unsigned long*, _a, 8); + } + } + while (1) + { + /* pull apart the last word processed and find the zero. */ + bitfields_t bx; + bx.v = x; +#if __mips64 + do_strlen_byte (0); + do_strlen_byte (1); + do_strlen_byte (2); + do_strlen_byte (3); + do_strlen_byte (4); + do_strlen_byte (5); + do_strlen_byte (6); +#else + do_strlen_byte (0); + do_strlen_byte (1); + do_strlen_byte (2); +#endif + /* last byte is zero */ + break; + } + return cnt; +} + +#undef do_strlen_byte +#undef do_strlen_word + +#if SMOKE_TEST_MIPS_STRLEN +#include <stdio.h> +char str1[] = "DHRYSTONE PROGRAM, 1'ST STRING"; +char str2[] = "DHRYSTONE PROGRAM, 2'ST STRING"; + +char str3[] = "another string"; +char str4[] = "another"; + +char str5[] = "somes tring"; +char str6[] = "somes_tring"; + +char str7[16], str8[16]; + +static char * +chk (unsigned long mine, unsigned long libs, int *errors) +{ + static char answer[1024]; + char *result = mine == libs ? "PASS" : "FAIL"; + sprintf (answer, "new_strlen=%d: lib_strlen=%d: %s!", mine, libs, result); + if (mine != libs) + (*errors)++; + return answer; +} + +int +main (int argc, char **argv) +{ + int errors = 0; + /* set -1 in one position */ + str6[5] = 0xff; + /* set zero in same position with junk in following 3 */ + str7[0] = str8[0] = 0; + str7[1] = 0xff; + str7[2] = 'a'; + str7[3] = 2; + str8[1] = 's'; + str8[2] = -2; + str8[3] = 0; + + fprintf (stderr, "========== mips_strlen%s test...\n", + argv[0] ? argv[0] : "unknown strlen"); +#define P(__x,__y) {\ + int a = my_strlen(__x + __y);\ + int b = (strlen)(__x + __y) /* library version */;\ + fprintf(stderr,"%s+%d: %s\n",#__x,__y,chk(a,b,&errors));\ + } + + P (str1, 0); + P (str1, 1); + P (str1, 2); + P (str1, 3); + + P (str2, 0); + P (str2, 1); + P (str2, 2); + P (str2, 3); + + P (str3, 0); + P (str3, 1); + P (str3, 2); + P (str3, 3); + + P (str4, 0); + P (str4, 1); + P (str4, 2); + P (str4, 3); + + P (str5, 0); + P (str5, 1); + P (str5, 2); + P (str5, 3); + + P (str6, 0); + P (str6, 1); + P (str6, 2); + P (str6, 3); + + P (str7, 0); + P (str7, 1); + P (str7, 2); + P (str7, 3); + + P (str8, 0); + P (str8, 1); + P (str8, 2); + P (str8, 3); + + return errors; +} +#endif diff --git a/libc/arch-mips64/syscalls/__accept4.S b/libc/arch-mips64/syscalls/__accept4.S new file mode 100644 index 0000000..ed9b6c7 --- /dev/null +++ b/libc/arch-mips64/syscalls/__accept4.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__accept4) + .set push + .set noreorder + li v0, __NR_accept4 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__accept4) +.hidden __accept4 diff --git a/libc/arch-mips64/syscalls/__brk.S b/libc/arch-mips64/syscalls/__brk.S new file mode 100644 index 0000000..e1f89c7 --- /dev/null +++ b/libc/arch-mips64/syscalls/__brk.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__brk) + .set push + .set noreorder + li v0, __NR_brk + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__brk) +.hidden __brk diff --git a/libc/arch-mips64/syscalls/__connect.S b/libc/arch-mips64/syscalls/__connect.S new file mode 100644 index 0000000..8c44464 --- /dev/null +++ b/libc/arch-mips64/syscalls/__connect.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__connect) + .set push + .set noreorder + li v0, __NR_connect + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__connect) +.hidden __connect diff --git a/libc/arch-mips64/syscalls/__epoll_pwait.S b/libc/arch-mips64/syscalls/__epoll_pwait.S new file mode 100644 index 0000000..5dfb380 --- /dev/null +++ b/libc/arch-mips64/syscalls/__epoll_pwait.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__epoll_pwait) + .set push + .set noreorder + li v0, __NR_epoll_pwait + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__epoll_pwait) +.hidden __epoll_pwait diff --git a/libc/arch-mips64/syscalls/__exit.S b/libc/arch-mips64/syscalls/__exit.S new file mode 100644 index 0000000..2d5e03d --- /dev/null +++ b/libc/arch-mips64/syscalls/__exit.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__exit) + .set push + .set noreorder + li v0, __NR_exit + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__exit) +.hidden __exit diff --git a/libc/arch-mips64/syscalls/__fadvise64.S b/libc/arch-mips64/syscalls/__fadvise64.S new file mode 100644 index 0000000..90aceb0 --- /dev/null +++ b/libc/arch-mips64/syscalls/__fadvise64.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__fadvise64) + .set push + .set noreorder + li v0, __NR_fadvise64 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__fadvise64) +.hidden __fadvise64 diff --git a/libc/arch-mips64/syscalls/__getcpu.S b/libc/arch-mips64/syscalls/__getcpu.S new file mode 100644 index 0000000..a16c21e --- /dev/null +++ b/libc/arch-mips64/syscalls/__getcpu.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getcpu) + .set push + .set noreorder + li v0, __NR_getcpu + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__getcpu) +.hidden __getcpu diff --git a/libc/arch-mips64/syscalls/__getcwd.S b/libc/arch-mips64/syscalls/__getcwd.S new file mode 100644 index 0000000..53eeb68 --- /dev/null +++ b/libc/arch-mips64/syscalls/__getcwd.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getcwd) + .set push + .set noreorder + li v0, __NR_getcwd + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__getcwd) +.hidden __getcwd diff --git a/libc/arch-mips64/syscalls/__getdents64.S b/libc/arch-mips64/syscalls/__getdents64.S new file mode 100644 index 0000000..3720b8e --- /dev/null +++ b/libc/arch-mips64/syscalls/__getdents64.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getdents64) + .set push + .set noreorder + li v0, __NR_getdents64 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__getdents64) +.hidden __getdents64 diff --git a/libc/arch-mips64/syscalls/__getpid.S b/libc/arch-mips64/syscalls/__getpid.S new file mode 100644 index 0000000..6d5d926 --- /dev/null +++ b/libc/arch-mips64/syscalls/__getpid.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getpid) + .set push + .set noreorder + li v0, __NR_getpid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__getpid) +.hidden __getpid diff --git a/libc/arch-mips64/syscalls/__getpriority.S b/libc/arch-mips64/syscalls/__getpriority.S new file mode 100644 index 0000000..19327ab --- /dev/null +++ b/libc/arch-mips64/syscalls/__getpriority.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__getpriority) + .set push + .set noreorder + li v0, __NR_getpriority + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__getpriority) +.hidden __getpriority diff --git a/libc/arch-mips64/syscalls/__ioctl.S b/libc/arch-mips64/syscalls/__ioctl.S new file mode 100644 index 0000000..7fad0d1 --- /dev/null +++ b/libc/arch-mips64/syscalls/__ioctl.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__ioctl) + .set push + .set noreorder + li v0, __NR_ioctl + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__ioctl) +.hidden __ioctl diff --git a/libc/arch-mips64/syscalls/__openat.S b/libc/arch-mips64/syscalls/__openat.S new file mode 100644 index 0000000..d3ac13a --- /dev/null +++ b/libc/arch-mips64/syscalls/__openat.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__openat) + .set push + .set noreorder + li v0, __NR_openat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__openat) +.hidden __openat diff --git a/libc/arch-mips64/syscalls/__ppoll.S b/libc/arch-mips64/syscalls/__ppoll.S new file mode 100644 index 0000000..4e6fb8a --- /dev/null +++ b/libc/arch-mips64/syscalls/__ppoll.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__ppoll) + .set push + .set noreorder + li v0, __NR_ppoll + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__ppoll) +.hidden __ppoll diff --git a/libc/arch-mips64/syscalls/__pselect6.S b/libc/arch-mips64/syscalls/__pselect6.S new file mode 100644 index 0000000..6d49d1c --- /dev/null +++ b/libc/arch-mips64/syscalls/__pselect6.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__pselect6) + .set push + .set noreorder + li v0, __NR_pselect6 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__pselect6) +.hidden __pselect6 diff --git a/libc/arch-mips64/syscalls/__ptrace.S b/libc/arch-mips64/syscalls/__ptrace.S new file mode 100644 index 0000000..5a3ce16 --- /dev/null +++ b/libc/arch-mips64/syscalls/__ptrace.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__ptrace) + .set push + .set noreorder + li v0, __NR_ptrace + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__ptrace) +.hidden __ptrace diff --git a/libc/arch-mips64/syscalls/__reboot.S b/libc/arch-mips64/syscalls/__reboot.S new file mode 100644 index 0000000..587310d --- /dev/null +++ b/libc/arch-mips64/syscalls/__reboot.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__reboot) + .set push + .set noreorder + li v0, __NR_reboot + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__reboot) +.hidden __reboot diff --git a/libc/arch-mips64/syscalls/__rt_sigaction.S b/libc/arch-mips64/syscalls/__rt_sigaction.S new file mode 100644 index 0000000..7dd3cae --- /dev/null +++ b/libc/arch-mips64/syscalls/__rt_sigaction.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigaction) + .set push + .set noreorder + li v0, __NR_rt_sigaction + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__rt_sigaction) +.hidden __rt_sigaction diff --git a/libc/arch-mips64/syscalls/__rt_sigpending.S b/libc/arch-mips64/syscalls/__rt_sigpending.S new file mode 100644 index 0000000..68ae39a --- /dev/null +++ b/libc/arch-mips64/syscalls/__rt_sigpending.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigpending) + .set push + .set noreorder + li v0, __NR_rt_sigpending + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__rt_sigpending) +.hidden __rt_sigpending diff --git a/libc/arch-mips64/syscalls/__rt_sigprocmask.S b/libc/arch-mips64/syscalls/__rt_sigprocmask.S new file mode 100644 index 0000000..54620e9 --- /dev/null +++ b/libc/arch-mips64/syscalls/__rt_sigprocmask.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigprocmask) + .set push + .set noreorder + li v0, __NR_rt_sigprocmask + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__rt_sigprocmask) +.hidden __rt_sigprocmask diff --git a/libc/arch-mips64/syscalls/__rt_sigsuspend.S b/libc/arch-mips64/syscalls/__rt_sigsuspend.S new file mode 100644 index 0000000..ea15def --- /dev/null +++ b/libc/arch-mips64/syscalls/__rt_sigsuspend.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigsuspend) + .set push + .set noreorder + li v0, __NR_rt_sigsuspend + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__rt_sigsuspend) +.hidden __rt_sigsuspend diff --git a/libc/arch-mips64/syscalls/__rt_sigtimedwait.S b/libc/arch-mips64/syscalls/__rt_sigtimedwait.S new file mode 100644 index 0000000..177f17c --- /dev/null +++ b/libc/arch-mips64/syscalls/__rt_sigtimedwait.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__rt_sigtimedwait) + .set push + .set noreorder + li v0, __NR_rt_sigtimedwait + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__rt_sigtimedwait) +.hidden __rt_sigtimedwait diff --git a/libc/arch-mips64/syscalls/__sched_getaffinity.S b/libc/arch-mips64/syscalls/__sched_getaffinity.S new file mode 100644 index 0000000..2081706 --- /dev/null +++ b/libc/arch-mips64/syscalls/__sched_getaffinity.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__sched_getaffinity) + .set push + .set noreorder + li v0, __NR_sched_getaffinity + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__sched_getaffinity) +.hidden __sched_getaffinity diff --git a/libc/arch-mips64/syscalls/__set_tid_address.S b/libc/arch-mips64/syscalls/__set_tid_address.S new file mode 100644 index 0000000..cd966dd --- /dev/null +++ b/libc/arch-mips64/syscalls/__set_tid_address.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__set_tid_address) + .set push + .set noreorder + li v0, __NR_set_tid_address + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__set_tid_address) +.hidden __set_tid_address diff --git a/libc/arch-mips64/syscalls/__set_tls.S b/libc/arch-mips64/syscalls/__set_tls.S new file mode 100644 index 0000000..cc98150 --- /dev/null +++ b/libc/arch-mips64/syscalls/__set_tls.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__set_tls) + .set push + .set noreorder + li v0, __NR_set_thread_area + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__set_tls) +.hidden __set_tls diff --git a/libc/arch-mips64/syscalls/__signalfd4.S b/libc/arch-mips64/syscalls/__signalfd4.S new file mode 100644 index 0000000..ea6eef1 --- /dev/null +++ b/libc/arch-mips64/syscalls/__signalfd4.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__signalfd4) + .set push + .set noreorder + li v0, __NR_signalfd4 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__signalfd4) +.hidden __signalfd4 diff --git a/libc/arch-mips64/syscalls/__socket.S b/libc/arch-mips64/syscalls/__socket.S new file mode 100644 index 0000000..a499359 --- /dev/null +++ b/libc/arch-mips64/syscalls/__socket.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__socket) + .set push + .set noreorder + li v0, __NR_socket + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__socket) +.hidden __socket diff --git a/libc/arch-mips64/syscalls/__timer_create.S b/libc/arch-mips64/syscalls/__timer_create.S new file mode 100644 index 0000000..c66d8f9 --- /dev/null +++ b/libc/arch-mips64/syscalls/__timer_create.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_create) + .set push + .set noreorder + li v0, __NR_timer_create + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__timer_create) +.hidden __timer_create diff --git a/libc/arch-mips64/syscalls/__timer_delete.S b/libc/arch-mips64/syscalls/__timer_delete.S new file mode 100644 index 0000000..45cf5e8 --- /dev/null +++ b/libc/arch-mips64/syscalls/__timer_delete.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_delete) + .set push + .set noreorder + li v0, __NR_timer_delete + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__timer_delete) +.hidden __timer_delete diff --git a/libc/arch-mips64/syscalls/__timer_getoverrun.S b/libc/arch-mips64/syscalls/__timer_getoverrun.S new file mode 100644 index 0000000..8a73160 --- /dev/null +++ b/libc/arch-mips64/syscalls/__timer_getoverrun.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_getoverrun) + .set push + .set noreorder + li v0, __NR_timer_getoverrun + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__timer_getoverrun) +.hidden __timer_getoverrun diff --git a/libc/arch-mips64/syscalls/__timer_gettime.S b/libc/arch-mips64/syscalls/__timer_gettime.S new file mode 100644 index 0000000..32ee5bf --- /dev/null +++ b/libc/arch-mips64/syscalls/__timer_gettime.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_gettime) + .set push + .set noreorder + li v0, __NR_timer_gettime + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__timer_gettime) +.hidden __timer_gettime diff --git a/libc/arch-mips64/syscalls/__timer_settime.S b/libc/arch-mips64/syscalls/__timer_settime.S new file mode 100644 index 0000000..59764d8 --- /dev/null +++ b/libc/arch-mips64/syscalls/__timer_settime.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__timer_settime) + .set push + .set noreorder + li v0, __NR_timer_settime + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__timer_settime) +.hidden __timer_settime diff --git a/libc/arch-mips64/syscalls/__waitid.S b/libc/arch-mips64/syscalls/__waitid.S new file mode 100644 index 0000000..5ee090d --- /dev/null +++ b/libc/arch-mips64/syscalls/__waitid.S @@ -0,0 +1,26 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(__waitid) + .set push + .set noreorder + li v0, __NR_waitid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(__waitid) +.hidden __waitid diff --git a/libc/arch-mips64/syscalls/_exit.S b/libc/arch-mips64/syscalls/_exit.S new file mode 100644 index 0000000..da5a2f7 --- /dev/null +++ b/libc/arch-mips64/syscalls/_exit.S @@ -0,0 +1,28 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(_exit) + .set push + .set noreorder + li v0, __NR_exit_group + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(_exit) + + .globl _Exit + .equ _Exit, _exit diff --git a/libc/arch-mips64/syscalls/_flush_cache.S b/libc/arch-mips64/syscalls/_flush_cache.S new file mode 100644 index 0000000..a9e4842 --- /dev/null +++ b/libc/arch-mips64/syscalls/_flush_cache.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(_flush_cache) + .set push + .set noreorder + li v0, __NR_cacheflush + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(_flush_cache) diff --git a/libc/arch-mips64/syscalls/acct.S b/libc/arch-mips64/syscalls/acct.S new file mode 100644 index 0000000..ff728dc --- /dev/null +++ b/libc/arch-mips64/syscalls/acct.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(acct) + .set push + .set noreorder + li v0, __NR_acct + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(acct) diff --git a/libc/arch-mips64/syscalls/bind.S b/libc/arch-mips64/syscalls/bind.S new file mode 100644 index 0000000..9c2b5b8 --- /dev/null +++ b/libc/arch-mips64/syscalls/bind.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(bind) + .set push + .set noreorder + li v0, __NR_bind + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(bind) diff --git a/libc/arch-mips64/syscalls/capget.S b/libc/arch-mips64/syscalls/capget.S new file mode 100644 index 0000000..9d05438 --- /dev/null +++ b/libc/arch-mips64/syscalls/capget.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(capget) + .set push + .set noreorder + li v0, __NR_capget + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(capget) diff --git a/libc/arch-mips64/syscalls/capset.S b/libc/arch-mips64/syscalls/capset.S new file mode 100644 index 0000000..e947028 --- /dev/null +++ b/libc/arch-mips64/syscalls/capset.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(capset) + .set push + .set noreorder + li v0, __NR_capset + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(capset) diff --git a/libc/arch-mips64/syscalls/chdir.S b/libc/arch-mips64/syscalls/chdir.S new file mode 100644 index 0000000..14b22c9 --- /dev/null +++ b/libc/arch-mips64/syscalls/chdir.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(chdir) + .set push + .set noreorder + li v0, __NR_chdir + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(chdir) diff --git a/libc/arch-mips64/syscalls/chroot.S b/libc/arch-mips64/syscalls/chroot.S new file mode 100644 index 0000000..e805f51 --- /dev/null +++ b/libc/arch-mips64/syscalls/chroot.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(chroot) + .set push + .set noreorder + li v0, __NR_chroot + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(chroot) diff --git a/libc/arch-mips64/syscalls/clock_getres.S b/libc/arch-mips64/syscalls/clock_getres.S new file mode 100644 index 0000000..41003a0 --- /dev/null +++ b/libc/arch-mips64/syscalls/clock_getres.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(clock_getres) + .set push + .set noreorder + li v0, __NR_clock_getres + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(clock_getres) diff --git a/libc/arch-mips64/syscalls/clock_gettime.S b/libc/arch-mips64/syscalls/clock_gettime.S new file mode 100644 index 0000000..0813560 --- /dev/null +++ b/libc/arch-mips64/syscalls/clock_gettime.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(clock_gettime) + .set push + .set noreorder + li v0, __NR_clock_gettime + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(clock_gettime) diff --git a/libc/arch-mips64/syscalls/clock_nanosleep.S b/libc/arch-mips64/syscalls/clock_nanosleep.S new file mode 100644 index 0000000..c958a10 --- /dev/null +++ b/libc/arch-mips64/syscalls/clock_nanosleep.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(clock_nanosleep) + .set push + .set noreorder + li v0, __NR_clock_nanosleep + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(clock_nanosleep) diff --git a/libc/arch-mips64/syscalls/clock_settime.S b/libc/arch-mips64/syscalls/clock_settime.S new file mode 100644 index 0000000..77b6ae4 --- /dev/null +++ b/libc/arch-mips64/syscalls/clock_settime.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(clock_settime) + .set push + .set noreorder + li v0, __NR_clock_settime + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(clock_settime) diff --git a/libc/arch-mips64/syscalls/close.S b/libc/arch-mips64/syscalls/close.S new file mode 100644 index 0000000..5e237dd --- /dev/null +++ b/libc/arch-mips64/syscalls/close.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(close) + .set push + .set noreorder + li v0, __NR_close + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(close) diff --git a/libc/arch-mips64/syscalls/delete_module.S b/libc/arch-mips64/syscalls/delete_module.S new file mode 100644 index 0000000..8396537 --- /dev/null +++ b/libc/arch-mips64/syscalls/delete_module.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(delete_module) + .set push + .set noreorder + li v0, __NR_delete_module + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(delete_module) diff --git a/libc/arch-mips64/syscalls/dup.S b/libc/arch-mips64/syscalls/dup.S new file mode 100644 index 0000000..d1ca5e7 --- /dev/null +++ b/libc/arch-mips64/syscalls/dup.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(dup) + .set push + .set noreorder + li v0, __NR_dup + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(dup) diff --git a/libc/arch-mips64/syscalls/dup3.S b/libc/arch-mips64/syscalls/dup3.S new file mode 100644 index 0000000..5601f31 --- /dev/null +++ b/libc/arch-mips64/syscalls/dup3.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(dup3) + .set push + .set noreorder + li v0, __NR_dup3 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(dup3) diff --git a/libc/arch-mips64/syscalls/epoll_create1.S b/libc/arch-mips64/syscalls/epoll_create1.S new file mode 100644 index 0000000..11f1ceb --- /dev/null +++ b/libc/arch-mips64/syscalls/epoll_create1.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(epoll_create1) + .set push + .set noreorder + li v0, __NR_epoll_create1 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(epoll_create1) diff --git a/libc/arch-mips64/syscalls/epoll_ctl.S b/libc/arch-mips64/syscalls/epoll_ctl.S new file mode 100644 index 0000000..9eba605 --- /dev/null +++ b/libc/arch-mips64/syscalls/epoll_ctl.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(epoll_ctl) + .set push + .set noreorder + li v0, __NR_epoll_ctl + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(epoll_ctl) diff --git a/libc/arch-mips64/syscalls/eventfd.S b/libc/arch-mips64/syscalls/eventfd.S new file mode 100644 index 0000000..5cd63e4 --- /dev/null +++ b/libc/arch-mips64/syscalls/eventfd.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(eventfd) + .set push + .set noreorder + li v0, __NR_eventfd2 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(eventfd) diff --git a/libc/arch-mips64/syscalls/execve.S b/libc/arch-mips64/syscalls/execve.S new file mode 100644 index 0000000..bcd5d60 --- /dev/null +++ b/libc/arch-mips64/syscalls/execve.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(execve) + .set push + .set noreorder + li v0, __NR_execve + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(execve) diff --git a/libc/arch-mips64/syscalls/faccessat.S b/libc/arch-mips64/syscalls/faccessat.S new file mode 100644 index 0000000..18bb800 --- /dev/null +++ b/libc/arch-mips64/syscalls/faccessat.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(faccessat) + .set push + .set noreorder + li v0, __NR_faccessat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(faccessat) diff --git a/libc/arch-mips64/syscalls/fallocate.S b/libc/arch-mips64/syscalls/fallocate.S new file mode 100644 index 0000000..c1ef0ed --- /dev/null +++ b/libc/arch-mips64/syscalls/fallocate.S @@ -0,0 +1,28 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fallocate) + .set push + .set noreorder + li v0, __NR_fallocate + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(fallocate) + + .globl fallocate64 + .equ fallocate64, fallocate diff --git a/libc/arch-mips64/syscalls/fchdir.S b/libc/arch-mips64/syscalls/fchdir.S new file mode 100644 index 0000000..e05625c --- /dev/null +++ b/libc/arch-mips64/syscalls/fchdir.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fchdir) + .set push + .set noreorder + li v0, __NR_fchdir + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(fchdir) diff --git a/libc/arch-mips64/syscalls/fchmod.S b/libc/arch-mips64/syscalls/fchmod.S new file mode 100644 index 0000000..a877b78 --- /dev/null +++ b/libc/arch-mips64/syscalls/fchmod.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fchmod) + .set push + .set noreorder + li v0, __NR_fchmod + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(fchmod) diff --git a/libc/arch-mips64/syscalls/fchmodat.S b/libc/arch-mips64/syscalls/fchmodat.S new file mode 100644 index 0000000..151492a --- /dev/null +++ b/libc/arch-mips64/syscalls/fchmodat.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fchmodat) + .set push + .set noreorder + li v0, __NR_fchmodat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(fchmodat) diff --git a/libc/arch-mips64/syscalls/fchown.S b/libc/arch-mips64/syscalls/fchown.S new file mode 100644 index 0000000..5dc33c0 --- /dev/null +++ b/libc/arch-mips64/syscalls/fchown.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fchown) + .set push + .set noreorder + li v0, __NR_fchown + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(fchown) diff --git a/libc/arch-mips64/syscalls/fchownat.S b/libc/arch-mips64/syscalls/fchownat.S new file mode 100644 index 0000000..f4cefe0 --- /dev/null +++ b/libc/arch-mips64/syscalls/fchownat.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fchownat) + .set push + .set noreorder + li v0, __NR_fchownat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(fchownat) diff --git a/libc/arch-mips64/syscalls/fcntl.S b/libc/arch-mips64/syscalls/fcntl.S new file mode 100644 index 0000000..dabc65b --- /dev/null +++ b/libc/arch-mips64/syscalls/fcntl.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fcntl) + .set push + .set noreorder + li v0, __NR_fcntl + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(fcntl) diff --git a/libc/arch-mips64/syscalls/fdatasync.S b/libc/arch-mips64/syscalls/fdatasync.S new file mode 100644 index 0000000..52be110 --- /dev/null +++ b/libc/arch-mips64/syscalls/fdatasync.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fdatasync) + .set push + .set noreorder + li v0, __NR_fdatasync + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(fdatasync) diff --git a/libc/arch-mips64/syscalls/fgetxattr.S b/libc/arch-mips64/syscalls/fgetxattr.S new file mode 100644 index 0000000..44c248a --- /dev/null +++ b/libc/arch-mips64/syscalls/fgetxattr.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fgetxattr) + .set push + .set noreorder + li v0, __NR_fgetxattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(fgetxattr) diff --git a/libc/arch-mips64/syscalls/flistxattr.S b/libc/arch-mips64/syscalls/flistxattr.S new file mode 100644 index 0000000..1d5b1b0 --- /dev/null +++ b/libc/arch-mips64/syscalls/flistxattr.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(flistxattr) + .set push + .set noreorder + li v0, __NR_flistxattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(flistxattr) diff --git a/libc/arch-mips64/syscalls/flock.S b/libc/arch-mips64/syscalls/flock.S new file mode 100644 index 0000000..d74a5db --- /dev/null +++ b/libc/arch-mips64/syscalls/flock.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(flock) + .set push + .set noreorder + li v0, __NR_flock + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(flock) diff --git a/libc/arch-mips64/syscalls/fremovexattr.S b/libc/arch-mips64/syscalls/fremovexattr.S new file mode 100644 index 0000000..417be4a --- /dev/null +++ b/libc/arch-mips64/syscalls/fremovexattr.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fremovexattr) + .set push + .set noreorder + li v0, __NR_fremovexattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(fremovexattr) diff --git a/libc/arch-mips64/syscalls/fsetxattr.S b/libc/arch-mips64/syscalls/fsetxattr.S new file mode 100644 index 0000000..0ad1f90 --- /dev/null +++ b/libc/arch-mips64/syscalls/fsetxattr.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fsetxattr) + .set push + .set noreorder + li v0, __NR_fsetxattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(fsetxattr) diff --git a/libc/arch-mips64/syscalls/fstat64.S b/libc/arch-mips64/syscalls/fstat64.S new file mode 100644 index 0000000..a14d51c --- /dev/null +++ b/libc/arch-mips64/syscalls/fstat64.S @@ -0,0 +1,28 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fstat64) + .set push + .set noreorder + li v0, __NR_fstat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(fstat64) + + .globl fstat + .equ fstat, fstat64 diff --git a/libc/arch-mips64/syscalls/fstatat64.S b/libc/arch-mips64/syscalls/fstatat64.S new file mode 100644 index 0000000..7888a43 --- /dev/null +++ b/libc/arch-mips64/syscalls/fstatat64.S @@ -0,0 +1,28 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fstatat64) + .set push + .set noreorder + li v0, __NR_newfstatat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(fstatat64) + + .globl fstatat + .equ fstatat, fstatat64 diff --git a/libc/arch-mips64/syscalls/fstatfs64.S b/libc/arch-mips64/syscalls/fstatfs64.S new file mode 100644 index 0000000..12e885c --- /dev/null +++ b/libc/arch-mips64/syscalls/fstatfs64.S @@ -0,0 +1,28 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fstatfs64) + .set push + .set noreorder + li v0, __NR_fstatfs + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(fstatfs64) + + .globl fstatfs + .equ fstatfs, fstatfs64 diff --git a/libc/arch-mips64/syscalls/fsync.S b/libc/arch-mips64/syscalls/fsync.S new file mode 100644 index 0000000..7056e36 --- /dev/null +++ b/libc/arch-mips64/syscalls/fsync.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(fsync) + .set push + .set noreorder + li v0, __NR_fsync + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(fsync) diff --git a/libc/arch-mips64/syscalls/ftruncate.S b/libc/arch-mips64/syscalls/ftruncate.S new file mode 100644 index 0000000..58b847b --- /dev/null +++ b/libc/arch-mips64/syscalls/ftruncate.S @@ -0,0 +1,28 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(ftruncate) + .set push + .set noreorder + li v0, __NR_ftruncate + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(ftruncate) + + .globl ftruncate64 + .equ ftruncate64, ftruncate diff --git a/libc/arch-mips64/syscalls/getegid.S b/libc/arch-mips64/syscalls/getegid.S new file mode 100644 index 0000000..439c6f0 --- /dev/null +++ b/libc/arch-mips64/syscalls/getegid.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getegid) + .set push + .set noreorder + li v0, __NR_getegid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getegid) diff --git a/libc/arch-mips64/syscalls/geteuid.S b/libc/arch-mips64/syscalls/geteuid.S new file mode 100644 index 0000000..5619dc6 --- /dev/null +++ b/libc/arch-mips64/syscalls/geteuid.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(geteuid) + .set push + .set noreorder + li v0, __NR_geteuid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(geteuid) diff --git a/libc/arch-mips64/syscalls/getgid.S b/libc/arch-mips64/syscalls/getgid.S new file mode 100644 index 0000000..777be1a --- /dev/null +++ b/libc/arch-mips64/syscalls/getgid.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getgid) + .set push + .set noreorder + li v0, __NR_getgid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getgid) diff --git a/libc/arch-mips64/syscalls/getgroups.S b/libc/arch-mips64/syscalls/getgroups.S new file mode 100644 index 0000000..93c4fa1 --- /dev/null +++ b/libc/arch-mips64/syscalls/getgroups.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getgroups) + .set push + .set noreorder + li v0, __NR_getgroups + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getgroups) diff --git a/libc/arch-mips64/syscalls/getitimer.S b/libc/arch-mips64/syscalls/getitimer.S new file mode 100644 index 0000000..fe78a97 --- /dev/null +++ b/libc/arch-mips64/syscalls/getitimer.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getitimer) + .set push + .set noreorder + li v0, __NR_getitimer + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getitimer) diff --git a/libc/arch-mips64/syscalls/getpeername.S b/libc/arch-mips64/syscalls/getpeername.S new file mode 100644 index 0000000..121f1a6 --- /dev/null +++ b/libc/arch-mips64/syscalls/getpeername.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getpeername) + .set push + .set noreorder + li v0, __NR_getpeername + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getpeername) diff --git a/libc/arch-mips64/syscalls/getpgid.S b/libc/arch-mips64/syscalls/getpgid.S new file mode 100644 index 0000000..19dc77f --- /dev/null +++ b/libc/arch-mips64/syscalls/getpgid.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getpgid) + .set push + .set noreorder + li v0, __NR_getpgid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getpgid) diff --git a/libc/arch-mips64/syscalls/getppid.S b/libc/arch-mips64/syscalls/getppid.S new file mode 100644 index 0000000..d00f309 --- /dev/null +++ b/libc/arch-mips64/syscalls/getppid.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getppid) + .set push + .set noreorder + li v0, __NR_getppid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getppid) diff --git a/libc/arch-mips64/syscalls/getresgid.S b/libc/arch-mips64/syscalls/getresgid.S new file mode 100644 index 0000000..18cb5a1 --- /dev/null +++ b/libc/arch-mips64/syscalls/getresgid.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getresgid) + .set push + .set noreorder + li v0, __NR_getresgid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getresgid) diff --git a/libc/arch-mips64/syscalls/getresuid.S b/libc/arch-mips64/syscalls/getresuid.S new file mode 100644 index 0000000..c217bf7 --- /dev/null +++ b/libc/arch-mips64/syscalls/getresuid.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getresuid) + .set push + .set noreorder + li v0, __NR_getresuid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getresuid) diff --git a/libc/arch-mips64/syscalls/getrlimit.S b/libc/arch-mips64/syscalls/getrlimit.S new file mode 100644 index 0000000..7576c17 --- /dev/null +++ b/libc/arch-mips64/syscalls/getrlimit.S @@ -0,0 +1,28 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getrlimit) + .set push + .set noreorder + li v0, __NR_getrlimit + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getrlimit) + + .globl getrlimit64 + .equ getrlimit64, getrlimit diff --git a/libc/arch-mips64/syscalls/getrusage.S b/libc/arch-mips64/syscalls/getrusage.S new file mode 100644 index 0000000..4bf557e --- /dev/null +++ b/libc/arch-mips64/syscalls/getrusage.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getrusage) + .set push + .set noreorder + li v0, __NR_getrusage + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getrusage) diff --git a/libc/arch-mips64/syscalls/getsid.S b/libc/arch-mips64/syscalls/getsid.S new file mode 100644 index 0000000..030c91d --- /dev/null +++ b/libc/arch-mips64/syscalls/getsid.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getsid) + .set push + .set noreorder + li v0, __NR_getsid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getsid) diff --git a/libc/arch-mips64/syscalls/getsockname.S b/libc/arch-mips64/syscalls/getsockname.S new file mode 100644 index 0000000..88a9426 --- /dev/null +++ b/libc/arch-mips64/syscalls/getsockname.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getsockname) + .set push + .set noreorder + li v0, __NR_getsockname + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getsockname) diff --git a/libc/arch-mips64/syscalls/getsockopt.S b/libc/arch-mips64/syscalls/getsockopt.S new file mode 100644 index 0000000..08ee634 --- /dev/null +++ b/libc/arch-mips64/syscalls/getsockopt.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getsockopt) + .set push + .set noreorder + li v0, __NR_getsockopt + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getsockopt) diff --git a/libc/arch-mips64/syscalls/gettimeofday.S b/libc/arch-mips64/syscalls/gettimeofday.S new file mode 100644 index 0000000..3a6d417 --- /dev/null +++ b/libc/arch-mips64/syscalls/gettimeofday.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(gettimeofday) + .set push + .set noreorder + li v0, __NR_gettimeofday + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(gettimeofday) diff --git a/libc/arch-mips64/syscalls/getuid.S b/libc/arch-mips64/syscalls/getuid.S new file mode 100644 index 0000000..3d5f940 --- /dev/null +++ b/libc/arch-mips64/syscalls/getuid.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getuid) + .set push + .set noreorder + li v0, __NR_getuid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getuid) diff --git a/libc/arch-mips64/syscalls/getxattr.S b/libc/arch-mips64/syscalls/getxattr.S new file mode 100644 index 0000000..1c443f2 --- /dev/null +++ b/libc/arch-mips64/syscalls/getxattr.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(getxattr) + .set push + .set noreorder + li v0, __NR_getxattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(getxattr) diff --git a/libc/arch-mips64/syscalls/init_module.S b/libc/arch-mips64/syscalls/init_module.S new file mode 100644 index 0000000..3e2f074 --- /dev/null +++ b/libc/arch-mips64/syscalls/init_module.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(init_module) + .set push + .set noreorder + li v0, __NR_init_module + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(init_module) diff --git a/libc/arch-mips64/syscalls/inotify_add_watch.S b/libc/arch-mips64/syscalls/inotify_add_watch.S new file mode 100644 index 0000000..bffdad8 --- /dev/null +++ b/libc/arch-mips64/syscalls/inotify_add_watch.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(inotify_add_watch) + .set push + .set noreorder + li v0, __NR_inotify_add_watch + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(inotify_add_watch) diff --git a/libc/arch-mips64/syscalls/inotify_init1.S b/libc/arch-mips64/syscalls/inotify_init1.S new file mode 100644 index 0000000..c70d101 --- /dev/null +++ b/libc/arch-mips64/syscalls/inotify_init1.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(inotify_init1) + .set push + .set noreorder + li v0, __NR_inotify_init1 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(inotify_init1) diff --git a/libc/arch-mips64/syscalls/inotify_rm_watch.S b/libc/arch-mips64/syscalls/inotify_rm_watch.S new file mode 100644 index 0000000..d893787 --- /dev/null +++ b/libc/arch-mips64/syscalls/inotify_rm_watch.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(inotify_rm_watch) + .set push + .set noreorder + li v0, __NR_inotify_rm_watch + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(inotify_rm_watch) diff --git a/libc/arch-mips64/syscalls/kill.S b/libc/arch-mips64/syscalls/kill.S new file mode 100644 index 0000000..475b615 --- /dev/null +++ b/libc/arch-mips64/syscalls/kill.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(kill) + .set push + .set noreorder + li v0, __NR_kill + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(kill) diff --git a/libc/arch-mips64/syscalls/klogctl.S b/libc/arch-mips64/syscalls/klogctl.S new file mode 100644 index 0000000..98b9f0b --- /dev/null +++ b/libc/arch-mips64/syscalls/klogctl.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(klogctl) + .set push + .set noreorder + li v0, __NR_syslog + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(klogctl) diff --git a/libc/arch-mips64/syscalls/lgetxattr.S b/libc/arch-mips64/syscalls/lgetxattr.S new file mode 100644 index 0000000..55d7c42 --- /dev/null +++ b/libc/arch-mips64/syscalls/lgetxattr.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(lgetxattr) + .set push + .set noreorder + li v0, __NR_lgetxattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(lgetxattr) diff --git a/libc/arch-mips64/syscalls/linkat.S b/libc/arch-mips64/syscalls/linkat.S new file mode 100644 index 0000000..df749eb --- /dev/null +++ b/libc/arch-mips64/syscalls/linkat.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(linkat) + .set push + .set noreorder + li v0, __NR_linkat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(linkat) diff --git a/libc/arch-mips64/syscalls/listen.S b/libc/arch-mips64/syscalls/listen.S new file mode 100644 index 0000000..195cade --- /dev/null +++ b/libc/arch-mips64/syscalls/listen.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(listen) + .set push + .set noreorder + li v0, __NR_listen + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(listen) diff --git a/libc/arch-mips64/syscalls/listxattr.S b/libc/arch-mips64/syscalls/listxattr.S new file mode 100644 index 0000000..30b0f2b --- /dev/null +++ b/libc/arch-mips64/syscalls/listxattr.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(listxattr) + .set push + .set noreorder + li v0, __NR_listxattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(listxattr) diff --git a/libc/arch-mips64/syscalls/llistxattr.S b/libc/arch-mips64/syscalls/llistxattr.S new file mode 100644 index 0000000..d3491163 --- /dev/null +++ b/libc/arch-mips64/syscalls/llistxattr.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(llistxattr) + .set push + .set noreorder + li v0, __NR_llistxattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(llistxattr) diff --git a/libc/arch-mips64/syscalls/lremovexattr.S b/libc/arch-mips64/syscalls/lremovexattr.S new file mode 100644 index 0000000..db4e4d3 --- /dev/null +++ b/libc/arch-mips64/syscalls/lremovexattr.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(lremovexattr) + .set push + .set noreorder + li v0, __NR_lremovexattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(lremovexattr) diff --git a/libc/arch-mips64/syscalls/lseek.S b/libc/arch-mips64/syscalls/lseek.S new file mode 100644 index 0000000..5c92d70 --- /dev/null +++ b/libc/arch-mips64/syscalls/lseek.S @@ -0,0 +1,28 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(lseek) + .set push + .set noreorder + li v0, __NR_lseek + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(lseek) + + .globl lseek64 + .equ lseek64, lseek diff --git a/libc/arch-mips64/syscalls/lsetxattr.S b/libc/arch-mips64/syscalls/lsetxattr.S new file mode 100644 index 0000000..c161eb3 --- /dev/null +++ b/libc/arch-mips64/syscalls/lsetxattr.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(lsetxattr) + .set push + .set noreorder + li v0, __NR_lsetxattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(lsetxattr) diff --git a/libc/arch-mips64/syscalls/madvise.S b/libc/arch-mips64/syscalls/madvise.S new file mode 100644 index 0000000..88f3830 --- /dev/null +++ b/libc/arch-mips64/syscalls/madvise.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(madvise) + .set push + .set noreorder + li v0, __NR_madvise + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(madvise) diff --git a/libc/arch-mips64/syscalls/mincore.S b/libc/arch-mips64/syscalls/mincore.S new file mode 100644 index 0000000..695c9b2 --- /dev/null +++ b/libc/arch-mips64/syscalls/mincore.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mincore) + .set push + .set noreorder + li v0, __NR_mincore + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(mincore) diff --git a/libc/arch-mips64/syscalls/mkdirat.S b/libc/arch-mips64/syscalls/mkdirat.S new file mode 100644 index 0000000..71cdfd1 --- /dev/null +++ b/libc/arch-mips64/syscalls/mkdirat.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mkdirat) + .set push + .set noreorder + li v0, __NR_mkdirat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(mkdirat) diff --git a/libc/arch-mips64/syscalls/mknodat.S b/libc/arch-mips64/syscalls/mknodat.S new file mode 100644 index 0000000..9943e49 --- /dev/null +++ b/libc/arch-mips64/syscalls/mknodat.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mknodat) + .set push + .set noreorder + li v0, __NR_mknodat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(mknodat) diff --git a/libc/arch-mips64/syscalls/mlock.S b/libc/arch-mips64/syscalls/mlock.S new file mode 100644 index 0000000..081f12b --- /dev/null +++ b/libc/arch-mips64/syscalls/mlock.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mlock) + .set push + .set noreorder + li v0, __NR_mlock + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(mlock) diff --git a/libc/arch-mips64/syscalls/mlockall.S b/libc/arch-mips64/syscalls/mlockall.S new file mode 100644 index 0000000..0e158f4 --- /dev/null +++ b/libc/arch-mips64/syscalls/mlockall.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mlockall) + .set push + .set noreorder + li v0, __NR_mlockall + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(mlockall) diff --git a/libc/arch-mips64/syscalls/mmap.S b/libc/arch-mips64/syscalls/mmap.S new file mode 100644 index 0000000..393271a --- /dev/null +++ b/libc/arch-mips64/syscalls/mmap.S @@ -0,0 +1,28 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mmap) + .set push + .set noreorder + li v0, __NR_mmap + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(mmap) + + .globl mmap64 + .equ mmap64, mmap diff --git a/libc/arch-mips64/syscalls/mount.S b/libc/arch-mips64/syscalls/mount.S new file mode 100644 index 0000000..50c7541 --- /dev/null +++ b/libc/arch-mips64/syscalls/mount.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mount) + .set push + .set noreorder + li v0, __NR_mount + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(mount) diff --git a/libc/arch-mips64/syscalls/mprotect.S b/libc/arch-mips64/syscalls/mprotect.S new file mode 100644 index 0000000..d755489 --- /dev/null +++ b/libc/arch-mips64/syscalls/mprotect.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mprotect) + .set push + .set noreorder + li v0, __NR_mprotect + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(mprotect) diff --git a/libc/arch-mips64/syscalls/mremap.S b/libc/arch-mips64/syscalls/mremap.S new file mode 100644 index 0000000..cf7f1de --- /dev/null +++ b/libc/arch-mips64/syscalls/mremap.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(mremap) + .set push + .set noreorder + li v0, __NR_mremap + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(mremap) diff --git a/libc/arch-mips64/syscalls/msync.S b/libc/arch-mips64/syscalls/msync.S new file mode 100644 index 0000000..efe31c1 --- /dev/null +++ b/libc/arch-mips64/syscalls/msync.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(msync) + .set push + .set noreorder + li v0, __NR_msync + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(msync) diff --git a/libc/arch-mips64/syscalls/munlock.S b/libc/arch-mips64/syscalls/munlock.S new file mode 100644 index 0000000..44b930a --- /dev/null +++ b/libc/arch-mips64/syscalls/munlock.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(munlock) + .set push + .set noreorder + li v0, __NR_munlock + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(munlock) diff --git a/libc/arch-mips64/syscalls/munlockall.S b/libc/arch-mips64/syscalls/munlockall.S new file mode 100644 index 0000000..ffeb5e1 --- /dev/null +++ b/libc/arch-mips64/syscalls/munlockall.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(munlockall) + .set push + .set noreorder + li v0, __NR_munlockall + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(munlockall) diff --git a/libc/arch-mips64/syscalls/munmap.S b/libc/arch-mips64/syscalls/munmap.S new file mode 100644 index 0000000..cd0c05c --- /dev/null +++ b/libc/arch-mips64/syscalls/munmap.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(munmap) + .set push + .set noreorder + li v0, __NR_munmap + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(munmap) diff --git a/libc/arch-mips64/syscalls/nanosleep.S b/libc/arch-mips64/syscalls/nanosleep.S new file mode 100644 index 0000000..bdaf256 --- /dev/null +++ b/libc/arch-mips64/syscalls/nanosleep.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(nanosleep) + .set push + .set noreorder + li v0, __NR_nanosleep + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(nanosleep) diff --git a/libc/arch-mips64/syscalls/personality.S b/libc/arch-mips64/syscalls/personality.S new file mode 100644 index 0000000..6a12c95 --- /dev/null +++ b/libc/arch-mips64/syscalls/personality.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(personality) + .set push + .set noreorder + li v0, __NR_personality + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(personality) diff --git a/libc/arch-mips64/syscalls/pipe2.S b/libc/arch-mips64/syscalls/pipe2.S new file mode 100644 index 0000000..1b08a45 --- /dev/null +++ b/libc/arch-mips64/syscalls/pipe2.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(pipe2) + .set push + .set noreorder + li v0, __NR_pipe2 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(pipe2) diff --git a/libc/arch-mips64/syscalls/prctl.S b/libc/arch-mips64/syscalls/prctl.S new file mode 100644 index 0000000..61bb7c2 --- /dev/null +++ b/libc/arch-mips64/syscalls/prctl.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(prctl) + .set push + .set noreorder + li v0, __NR_prctl + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(prctl) diff --git a/libc/arch-mips64/syscalls/pread64.S b/libc/arch-mips64/syscalls/pread64.S new file mode 100644 index 0000000..90e0612 --- /dev/null +++ b/libc/arch-mips64/syscalls/pread64.S @@ -0,0 +1,28 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(pread64) + .set push + .set noreorder + li v0, __NR_pread64 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(pread64) + + .globl pread + .equ pread, pread64 diff --git a/libc/arch-mips64/syscalls/prlimit64.S b/libc/arch-mips64/syscalls/prlimit64.S new file mode 100644 index 0000000..5f0ba1d --- /dev/null +++ b/libc/arch-mips64/syscalls/prlimit64.S @@ -0,0 +1,28 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(prlimit64) + .set push + .set noreorder + li v0, __NR_prlimit64 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(prlimit64) + + .globl prlimit + .equ prlimit, prlimit64 diff --git a/libc/arch-mips64/syscalls/pwrite64.S b/libc/arch-mips64/syscalls/pwrite64.S new file mode 100644 index 0000000..e34f8db --- /dev/null +++ b/libc/arch-mips64/syscalls/pwrite64.S @@ -0,0 +1,28 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(pwrite64) + .set push + .set noreorder + li v0, __NR_pwrite64 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(pwrite64) + + .globl pwrite + .equ pwrite, pwrite64 diff --git a/libc/arch-mips64/syscalls/read.S b/libc/arch-mips64/syscalls/read.S new file mode 100644 index 0000000..74d39df --- /dev/null +++ b/libc/arch-mips64/syscalls/read.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(read) + .set push + .set noreorder + li v0, __NR_read + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(read) diff --git a/libc/arch-mips64/syscalls/readahead.S b/libc/arch-mips64/syscalls/readahead.S new file mode 100644 index 0000000..ae511d9 --- /dev/null +++ b/libc/arch-mips64/syscalls/readahead.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(readahead) + .set push + .set noreorder + li v0, __NR_readahead + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(readahead) diff --git a/libc/arch-mips64/syscalls/readlinkat.S b/libc/arch-mips64/syscalls/readlinkat.S new file mode 100644 index 0000000..473a946 --- /dev/null +++ b/libc/arch-mips64/syscalls/readlinkat.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(readlinkat) + .set push + .set noreorder + li v0, __NR_readlinkat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(readlinkat) diff --git a/libc/arch-mips64/syscalls/readv.S b/libc/arch-mips64/syscalls/readv.S new file mode 100644 index 0000000..daa800c --- /dev/null +++ b/libc/arch-mips64/syscalls/readv.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(readv) + .set push + .set noreorder + li v0, __NR_readv + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(readv) diff --git a/libc/arch-mips64/syscalls/recvfrom.S b/libc/arch-mips64/syscalls/recvfrom.S new file mode 100644 index 0000000..4c9b5fa --- /dev/null +++ b/libc/arch-mips64/syscalls/recvfrom.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(recvfrom) + .set push + .set noreorder + li v0, __NR_recvfrom + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(recvfrom) diff --git a/libc/arch-mips64/syscalls/recvmmsg.S b/libc/arch-mips64/syscalls/recvmmsg.S new file mode 100644 index 0000000..817250c --- /dev/null +++ b/libc/arch-mips64/syscalls/recvmmsg.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(recvmmsg) + .set push + .set noreorder + li v0, __NR_recvmmsg + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(recvmmsg) diff --git a/libc/arch-mips64/syscalls/recvmsg.S b/libc/arch-mips64/syscalls/recvmsg.S new file mode 100644 index 0000000..877899d --- /dev/null +++ b/libc/arch-mips64/syscalls/recvmsg.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(recvmsg) + .set push + .set noreorder + li v0, __NR_recvmsg + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(recvmsg) diff --git a/libc/arch-mips64/syscalls/removexattr.S b/libc/arch-mips64/syscalls/removexattr.S new file mode 100644 index 0000000..c9d8a0e --- /dev/null +++ b/libc/arch-mips64/syscalls/removexattr.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(removexattr) + .set push + .set noreorder + li v0, __NR_removexattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(removexattr) diff --git a/libc/arch-mips64/syscalls/renameat.S b/libc/arch-mips64/syscalls/renameat.S new file mode 100644 index 0000000..16b9333 --- /dev/null +++ b/libc/arch-mips64/syscalls/renameat.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(renameat) + .set push + .set noreorder + li v0, __NR_renameat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(renameat) diff --git a/libc/arch-mips64/syscalls/sched_get_priority_max.S b/libc/arch-mips64/syscalls/sched_get_priority_max.S new file mode 100644 index 0000000..67e2675 --- /dev/null +++ b/libc/arch-mips64/syscalls/sched_get_priority_max.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_get_priority_max) + .set push + .set noreorder + li v0, __NR_sched_get_priority_max + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sched_get_priority_max) diff --git a/libc/arch-mips64/syscalls/sched_get_priority_min.S b/libc/arch-mips64/syscalls/sched_get_priority_min.S new file mode 100644 index 0000000..957f523 --- /dev/null +++ b/libc/arch-mips64/syscalls/sched_get_priority_min.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_get_priority_min) + .set push + .set noreorder + li v0, __NR_sched_get_priority_min + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sched_get_priority_min) diff --git a/libc/arch-mips64/syscalls/sched_getparam.S b/libc/arch-mips64/syscalls/sched_getparam.S new file mode 100644 index 0000000..77bb4eb --- /dev/null +++ b/libc/arch-mips64/syscalls/sched_getparam.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_getparam) + .set push + .set noreorder + li v0, __NR_sched_getparam + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sched_getparam) diff --git a/libc/arch-mips64/syscalls/sched_getscheduler.S b/libc/arch-mips64/syscalls/sched_getscheduler.S new file mode 100644 index 0000000..324fa21 --- /dev/null +++ b/libc/arch-mips64/syscalls/sched_getscheduler.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_getscheduler) + .set push + .set noreorder + li v0, __NR_sched_getscheduler + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sched_getscheduler) diff --git a/libc/arch-mips64/syscalls/sched_rr_get_interval.S b/libc/arch-mips64/syscalls/sched_rr_get_interval.S new file mode 100644 index 0000000..3019554 --- /dev/null +++ b/libc/arch-mips64/syscalls/sched_rr_get_interval.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_rr_get_interval) + .set push + .set noreorder + li v0, __NR_sched_rr_get_interval + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sched_rr_get_interval) diff --git a/libc/arch-mips64/syscalls/sched_setaffinity.S b/libc/arch-mips64/syscalls/sched_setaffinity.S new file mode 100644 index 0000000..1520902 --- /dev/null +++ b/libc/arch-mips64/syscalls/sched_setaffinity.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_setaffinity) + .set push + .set noreorder + li v0, __NR_sched_setaffinity + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sched_setaffinity) diff --git a/libc/arch-mips64/syscalls/sched_setparam.S b/libc/arch-mips64/syscalls/sched_setparam.S new file mode 100644 index 0000000..a37b15c --- /dev/null +++ b/libc/arch-mips64/syscalls/sched_setparam.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_setparam) + .set push + .set noreorder + li v0, __NR_sched_setparam + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sched_setparam) diff --git a/libc/arch-mips64/syscalls/sched_setscheduler.S b/libc/arch-mips64/syscalls/sched_setscheduler.S new file mode 100644 index 0000000..ea4c6c4 --- /dev/null +++ b/libc/arch-mips64/syscalls/sched_setscheduler.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_setscheduler) + .set push + .set noreorder + li v0, __NR_sched_setscheduler + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sched_setscheduler) diff --git a/libc/arch-mips64/syscalls/sched_yield.S b/libc/arch-mips64/syscalls/sched_yield.S new file mode 100644 index 0000000..5d86ea5 --- /dev/null +++ b/libc/arch-mips64/syscalls/sched_yield.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sched_yield) + .set push + .set noreorder + li v0, __NR_sched_yield + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sched_yield) diff --git a/libc/arch-mips64/syscalls/sendfile.S b/libc/arch-mips64/syscalls/sendfile.S new file mode 100644 index 0000000..f330242 --- /dev/null +++ b/libc/arch-mips64/syscalls/sendfile.S @@ -0,0 +1,28 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sendfile) + .set push + .set noreorder + li v0, __NR_sendfile + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sendfile) + + .globl sendfile64 + .equ sendfile64, sendfile diff --git a/libc/arch-mips64/syscalls/sendmmsg.S b/libc/arch-mips64/syscalls/sendmmsg.S new file mode 100644 index 0000000..4a8d855 --- /dev/null +++ b/libc/arch-mips64/syscalls/sendmmsg.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sendmmsg) + .set push + .set noreorder + li v0, __NR_sendmmsg + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sendmmsg) diff --git a/libc/arch-mips64/syscalls/sendmsg.S b/libc/arch-mips64/syscalls/sendmsg.S new file mode 100644 index 0000000..519dce4 --- /dev/null +++ b/libc/arch-mips64/syscalls/sendmsg.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sendmsg) + .set push + .set noreorder + li v0, __NR_sendmsg + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sendmsg) diff --git a/libc/arch-mips64/syscalls/sendto.S b/libc/arch-mips64/syscalls/sendto.S new file mode 100644 index 0000000..84efc09 --- /dev/null +++ b/libc/arch-mips64/syscalls/sendto.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sendto) + .set push + .set noreorder + li v0, __NR_sendto + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sendto) diff --git a/libc/arch-mips64/syscalls/setfsgid.S b/libc/arch-mips64/syscalls/setfsgid.S new file mode 100644 index 0000000..db1bd7f --- /dev/null +++ b/libc/arch-mips64/syscalls/setfsgid.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setfsgid) + .set push + .set noreorder + li v0, __NR_setfsgid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setfsgid) diff --git a/libc/arch-mips64/syscalls/setfsuid.S b/libc/arch-mips64/syscalls/setfsuid.S new file mode 100644 index 0000000..4254b18 --- /dev/null +++ b/libc/arch-mips64/syscalls/setfsuid.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setfsuid) + .set push + .set noreorder + li v0, __NR_setfsuid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setfsuid) diff --git a/libc/arch-mips64/syscalls/setgid.S b/libc/arch-mips64/syscalls/setgid.S new file mode 100644 index 0000000..166a6d6 --- /dev/null +++ b/libc/arch-mips64/syscalls/setgid.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setgid) + .set push + .set noreorder + li v0, __NR_setgid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setgid) diff --git a/libc/arch-mips64/syscalls/setgroups.S b/libc/arch-mips64/syscalls/setgroups.S new file mode 100644 index 0000000..24649f7 --- /dev/null +++ b/libc/arch-mips64/syscalls/setgroups.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setgroups) + .set push + .set noreorder + li v0, __NR_setgroups + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setgroups) diff --git a/libc/arch-mips64/syscalls/setitimer.S b/libc/arch-mips64/syscalls/setitimer.S new file mode 100644 index 0000000..5764573 --- /dev/null +++ b/libc/arch-mips64/syscalls/setitimer.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setitimer) + .set push + .set noreorder + li v0, __NR_setitimer + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setitimer) diff --git a/libc/arch-mips64/syscalls/setns.S b/libc/arch-mips64/syscalls/setns.S new file mode 100644 index 0000000..6b6178f --- /dev/null +++ b/libc/arch-mips64/syscalls/setns.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setns) + .set push + .set noreorder + li v0, __NR_setns + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setns) diff --git a/libc/arch-mips64/syscalls/setpgid.S b/libc/arch-mips64/syscalls/setpgid.S new file mode 100644 index 0000000..233f784 --- /dev/null +++ b/libc/arch-mips64/syscalls/setpgid.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setpgid) + .set push + .set noreorder + li v0, __NR_setpgid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setpgid) diff --git a/libc/arch-mips64/syscalls/setpriority.S b/libc/arch-mips64/syscalls/setpriority.S new file mode 100644 index 0000000..d88a2ff --- /dev/null +++ b/libc/arch-mips64/syscalls/setpriority.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setpriority) + .set push + .set noreorder + li v0, __NR_setpriority + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setpriority) diff --git a/libc/arch-mips64/syscalls/setregid.S b/libc/arch-mips64/syscalls/setregid.S new file mode 100644 index 0000000..c82b4fd --- /dev/null +++ b/libc/arch-mips64/syscalls/setregid.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setregid) + .set push + .set noreorder + li v0, __NR_setregid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setregid) diff --git a/libc/arch-mips64/syscalls/setresgid.S b/libc/arch-mips64/syscalls/setresgid.S new file mode 100644 index 0000000..90b2939 --- /dev/null +++ b/libc/arch-mips64/syscalls/setresgid.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setresgid) + .set push + .set noreorder + li v0, __NR_setresgid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setresgid) diff --git a/libc/arch-mips64/syscalls/setresuid.S b/libc/arch-mips64/syscalls/setresuid.S new file mode 100644 index 0000000..501ac5d --- /dev/null +++ b/libc/arch-mips64/syscalls/setresuid.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setresuid) + .set push + .set noreorder + li v0, __NR_setresuid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setresuid) diff --git a/libc/arch-mips64/syscalls/setreuid.S b/libc/arch-mips64/syscalls/setreuid.S new file mode 100644 index 0000000..1b3203c --- /dev/null +++ b/libc/arch-mips64/syscalls/setreuid.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setreuid) + .set push + .set noreorder + li v0, __NR_setreuid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setreuid) diff --git a/libc/arch-mips64/syscalls/setrlimit.S b/libc/arch-mips64/syscalls/setrlimit.S new file mode 100644 index 0000000..0e5e80e --- /dev/null +++ b/libc/arch-mips64/syscalls/setrlimit.S @@ -0,0 +1,28 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setrlimit) + .set push + .set noreorder + li v0, __NR_setrlimit + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setrlimit) + + .globl setrlimit64 + .equ setrlimit64, setrlimit diff --git a/libc/arch-mips64/syscalls/setsid.S b/libc/arch-mips64/syscalls/setsid.S new file mode 100644 index 0000000..6d872d3 --- /dev/null +++ b/libc/arch-mips64/syscalls/setsid.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setsid) + .set push + .set noreorder + li v0, __NR_setsid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setsid) diff --git a/libc/arch-mips64/syscalls/setsockopt.S b/libc/arch-mips64/syscalls/setsockopt.S new file mode 100644 index 0000000..b2fc736 --- /dev/null +++ b/libc/arch-mips64/syscalls/setsockopt.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setsockopt) + .set push + .set noreorder + li v0, __NR_setsockopt + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setsockopt) diff --git a/libc/arch-mips64/syscalls/settimeofday.S b/libc/arch-mips64/syscalls/settimeofday.S new file mode 100644 index 0000000..9f1acfe --- /dev/null +++ b/libc/arch-mips64/syscalls/settimeofday.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(settimeofday) + .set push + .set noreorder + li v0, __NR_settimeofday + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(settimeofday) diff --git a/libc/arch-mips64/syscalls/setuid.S b/libc/arch-mips64/syscalls/setuid.S new file mode 100644 index 0000000..dcd39ff --- /dev/null +++ b/libc/arch-mips64/syscalls/setuid.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setuid) + .set push + .set noreorder + li v0, __NR_setuid + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setuid) diff --git a/libc/arch-mips64/syscalls/setxattr.S b/libc/arch-mips64/syscalls/setxattr.S new file mode 100644 index 0000000..4a1b87a --- /dev/null +++ b/libc/arch-mips64/syscalls/setxattr.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(setxattr) + .set push + .set noreorder + li v0, __NR_setxattr + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(setxattr) diff --git a/libc/arch-mips64/syscalls/shutdown.S b/libc/arch-mips64/syscalls/shutdown.S new file mode 100644 index 0000000..d654288 --- /dev/null +++ b/libc/arch-mips64/syscalls/shutdown.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(shutdown) + .set push + .set noreorder + li v0, __NR_shutdown + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(shutdown) diff --git a/libc/arch-mips64/syscalls/sigaltstack.S b/libc/arch-mips64/syscalls/sigaltstack.S new file mode 100644 index 0000000..92778c1 --- /dev/null +++ b/libc/arch-mips64/syscalls/sigaltstack.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sigaltstack) + .set push + .set noreorder + li v0, __NR_sigaltstack + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sigaltstack) diff --git a/libc/arch-mips64/syscalls/socketpair.S b/libc/arch-mips64/syscalls/socketpair.S new file mode 100644 index 0000000..8fbf7a8 --- /dev/null +++ b/libc/arch-mips64/syscalls/socketpair.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(socketpair) + .set push + .set noreorder + li v0, __NR_socketpair + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(socketpair) diff --git a/libc/arch-mips64/syscalls/splice.S b/libc/arch-mips64/syscalls/splice.S new file mode 100644 index 0000000..ea745cf --- /dev/null +++ b/libc/arch-mips64/syscalls/splice.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(splice) + .set push + .set noreorder + li v0, __NR_splice + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(splice) diff --git a/libc/arch-mips64/syscalls/statfs64.S b/libc/arch-mips64/syscalls/statfs64.S new file mode 100644 index 0000000..74351f7 --- /dev/null +++ b/libc/arch-mips64/syscalls/statfs64.S @@ -0,0 +1,28 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(statfs64) + .set push + .set noreorder + li v0, __NR_statfs + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(statfs64) + + .globl statfs + .equ statfs, statfs64 diff --git a/libc/arch-mips64/syscalls/swapoff.S b/libc/arch-mips64/syscalls/swapoff.S new file mode 100644 index 0000000..8c0048d --- /dev/null +++ b/libc/arch-mips64/syscalls/swapoff.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(swapoff) + .set push + .set noreorder + li v0, __NR_swapoff + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(swapoff) diff --git a/libc/arch-mips64/syscalls/swapon.S b/libc/arch-mips64/syscalls/swapon.S new file mode 100644 index 0000000..e8f6ff2 --- /dev/null +++ b/libc/arch-mips64/syscalls/swapon.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(swapon) + .set push + .set noreorder + li v0, __NR_swapon + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(swapon) diff --git a/libc/arch-mips64/syscalls/symlinkat.S b/libc/arch-mips64/syscalls/symlinkat.S new file mode 100644 index 0000000..592b8e2 --- /dev/null +++ b/libc/arch-mips64/syscalls/symlinkat.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(symlinkat) + .set push + .set noreorder + li v0, __NR_symlinkat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(symlinkat) diff --git a/libc/arch-mips64/syscalls/sync.S b/libc/arch-mips64/syscalls/sync.S new file mode 100644 index 0000000..8997c1b --- /dev/null +++ b/libc/arch-mips64/syscalls/sync.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sync) + .set push + .set noreorder + li v0, __NR_sync + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sync) diff --git a/libc/arch-mips64/syscalls/sysinfo.S b/libc/arch-mips64/syscalls/sysinfo.S new file mode 100644 index 0000000..a54e158 --- /dev/null +++ b/libc/arch-mips64/syscalls/sysinfo.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(sysinfo) + .set push + .set noreorder + li v0, __NR_sysinfo + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(sysinfo) diff --git a/libc/arch-mips64/syscalls/tee.S b/libc/arch-mips64/syscalls/tee.S new file mode 100644 index 0000000..99cf84b --- /dev/null +++ b/libc/arch-mips64/syscalls/tee.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(tee) + .set push + .set noreorder + li v0, __NR_tee + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(tee) diff --git a/libc/arch-mips64/syscalls/tgkill.S b/libc/arch-mips64/syscalls/tgkill.S new file mode 100644 index 0000000..f37f792 --- /dev/null +++ b/libc/arch-mips64/syscalls/tgkill.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(tgkill) + .set push + .set noreorder + li v0, __NR_tgkill + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(tgkill) diff --git a/libc/arch-mips64/syscalls/timerfd_create.S b/libc/arch-mips64/syscalls/timerfd_create.S new file mode 100644 index 0000000..0e53a15 --- /dev/null +++ b/libc/arch-mips64/syscalls/timerfd_create.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(timerfd_create) + .set push + .set noreorder + li v0, __NR_timerfd_create + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(timerfd_create) diff --git a/libc/arch-mips64/syscalls/timerfd_gettime.S b/libc/arch-mips64/syscalls/timerfd_gettime.S new file mode 100644 index 0000000..26d6832 --- /dev/null +++ b/libc/arch-mips64/syscalls/timerfd_gettime.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(timerfd_gettime) + .set push + .set noreorder + li v0, __NR_timerfd_gettime + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(timerfd_gettime) diff --git a/libc/arch-mips64/syscalls/timerfd_settime.S b/libc/arch-mips64/syscalls/timerfd_settime.S new file mode 100644 index 0000000..b06290e --- /dev/null +++ b/libc/arch-mips64/syscalls/timerfd_settime.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(timerfd_settime) + .set push + .set noreorder + li v0, __NR_timerfd_settime + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(timerfd_settime) diff --git a/libc/arch-mips64/syscalls/times.S b/libc/arch-mips64/syscalls/times.S new file mode 100644 index 0000000..fa7f64f --- /dev/null +++ b/libc/arch-mips64/syscalls/times.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(times) + .set push + .set noreorder + li v0, __NR_times + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(times) diff --git a/libc/arch-mips64/syscalls/truncate.S b/libc/arch-mips64/syscalls/truncate.S new file mode 100644 index 0000000..fb3b7eb --- /dev/null +++ b/libc/arch-mips64/syscalls/truncate.S @@ -0,0 +1,28 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(truncate) + .set push + .set noreorder + li v0, __NR_truncate + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(truncate) + + .globl truncate64 + .equ truncate64, truncate diff --git a/libc/arch-mips64/syscalls/umask.S b/libc/arch-mips64/syscalls/umask.S new file mode 100644 index 0000000..9349030 --- /dev/null +++ b/libc/arch-mips64/syscalls/umask.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(umask) + .set push + .set noreorder + li v0, __NR_umask + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(umask) diff --git a/libc/arch-mips64/syscalls/umount2.S b/libc/arch-mips64/syscalls/umount2.S new file mode 100644 index 0000000..cc9ad16 --- /dev/null +++ b/libc/arch-mips64/syscalls/umount2.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(umount2) + .set push + .set noreorder + li v0, __NR_umount2 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(umount2) diff --git a/libc/arch-mips64/syscalls/uname.S b/libc/arch-mips64/syscalls/uname.S new file mode 100644 index 0000000..16157da --- /dev/null +++ b/libc/arch-mips64/syscalls/uname.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(uname) + .set push + .set noreorder + li v0, __NR_uname + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(uname) diff --git a/libc/arch-mips64/syscalls/unlinkat.S b/libc/arch-mips64/syscalls/unlinkat.S new file mode 100644 index 0000000..4b11679 --- /dev/null +++ b/libc/arch-mips64/syscalls/unlinkat.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(unlinkat) + .set push + .set noreorder + li v0, __NR_unlinkat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(unlinkat) diff --git a/libc/arch-mips64/syscalls/unshare.S b/libc/arch-mips64/syscalls/unshare.S new file mode 100644 index 0000000..2c82fea --- /dev/null +++ b/libc/arch-mips64/syscalls/unshare.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(unshare) + .set push + .set noreorder + li v0, __NR_unshare + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(unshare) diff --git a/libc/arch-mips64/syscalls/utimensat.S b/libc/arch-mips64/syscalls/utimensat.S new file mode 100644 index 0000000..48da938 --- /dev/null +++ b/libc/arch-mips64/syscalls/utimensat.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(utimensat) + .set push + .set noreorder + li v0, __NR_utimensat + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(utimensat) diff --git a/libc/arch-mips64/syscalls/vmsplice.S b/libc/arch-mips64/syscalls/vmsplice.S new file mode 100644 index 0000000..3bcae74 --- /dev/null +++ b/libc/arch-mips64/syscalls/vmsplice.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(vmsplice) + .set push + .set noreorder + li v0, __NR_vmsplice + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(vmsplice) diff --git a/libc/arch-mips64/syscalls/wait4.S b/libc/arch-mips64/syscalls/wait4.S new file mode 100644 index 0000000..f9c3974 --- /dev/null +++ b/libc/arch-mips64/syscalls/wait4.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(wait4) + .set push + .set noreorder + li v0, __NR_wait4 + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(wait4) diff --git a/libc/arch-mips64/syscalls/write.S b/libc/arch-mips64/syscalls/write.S new file mode 100644 index 0000000..ef9b19e --- /dev/null +++ b/libc/arch-mips64/syscalls/write.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(write) + .set push + .set noreorder + li v0, __NR_write + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(write) diff --git a/libc/arch-mips64/syscalls/writev.S b/libc/arch-mips64/syscalls/writev.S new file mode 100644 index 0000000..d103d71 --- /dev/null +++ b/libc/arch-mips64/syscalls/writev.S @@ -0,0 +1,25 @@ +/* Generated by gensyscalls.py. Do not edit. */ + +#include <private/bionic_asm.h> + +ENTRY(writev) + .set push + .set noreorder + li v0, __NR_writev + syscall + bnez a3, 1f + move a0, v0 + j ra + nop +1: + move t0, ra + bal 2f + nop +2: + .cpsetup ra, t1, 2b + LA t9,__set_errno_internal + .cpreturn + j t9 + move ra, t0 + .set pop +END(writev) |