18 files changed, 1971 insertions, 0 deletions
diff --git a/libc/kernel/arch-arm/asm/arch/board-perseus2.h b/libc/kernel/arch-arm/asm/arch/board-perseus2.h
new file mode 100644
index 0000000..c6c5413
--- /dev/null
+++ b/libc/kernel/arch-arm/asm/arch/board-perseus2.h
@@ -0,0 +1,27 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef __ASM_ARCH_OMAP_PERSEUS2_H
+#define __ASM_ARCH_OMAP_PERSEUS2_H
+
+#include <asm/arch/fpga.h>
+
+#ifndef OMAP_SDRAM_DEVICE
+#define OMAP_SDRAM_DEVICE D256M_1X16_4B
+#endif
+
+#define MAXIRQNUM IH_BOARD_BASE
+#define MAXFIQNUM MAXIRQNUM
+#define MAXSWINUM MAXIRQNUM
+
+#define NR_IRQS (MAXIRQNUM + 1)
+
+#endif
diff --git a/libc/kernel/arch-arm/asm/arch/board.h b/libc/kernel/arch-arm/asm/arch/board.h
new file mode 100644
index 0000000..a7a4c66
--- /dev/null
+++ b/libc/kernel/arch-arm/asm/arch/board.h
@@ -0,0 +1,163 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef _OMAP_BOARD_H
+#define _OMAP_BOARD_H
+
+#include <linux/types.h>
+
+#include <asm/arch/gpio-switch.h>
+
+#define OMAP_TAG_CLOCK 0x4f01
+#define OMAP_TAG_MMC 0x4f02
+#define OMAP_TAG_SERIAL_CONSOLE 0x4f03
+#define OMAP_TAG_USB 0x4f04
+#define OMAP_TAG_LCD 0x4f05
+#define OMAP_TAG_GPIO_SWITCH 0x4f06
+#define OMAP_TAG_UART 0x4f07
+#define OMAP_TAG_FBMEM 0x4f08
+#define OMAP_TAG_STI_CONSOLE 0x4f09
+#define OMAP_TAG_CAMERA_SENSOR 0x4f0a
+#define OMAP_TAG_BT 0x4f0b
+
+#define OMAP_TAG_BOOT_REASON 0x4f80
+#define OMAP_TAG_FLASH_PART 0x4f81
+#define OMAP_TAG_VERSION_STR 0x4f82
+
+struct omap_clock_config {
+
+ u8 system_clock_type;
+};
+
+struct omap_mmc_conf {
+ unsigned enabled:1;
+
+ unsigned nomux:1;
+
+ unsigned cover:1;
+
+ unsigned wire4:1;
+ s16 power_pin;
+ s16 switch_pin;
+ s16 wp_pin;
+};
+
+struct omap_mmc_config {
+ struct omap_mmc_conf mmc[2];
+};
+
+struct omap_serial_console_config {
+ u8 console_uart;
+ u32 console_speed;
+};
+
+struct omap_sti_console_config {
+ unsigned enable:1;
+ u8 channel;
+};
+
+struct omap_camera_sensor_config {
+ u16 reset_gpio;
+ int (*power_on)(void * data);
+ int (*power_off)(void * data);
+};
+
+struct omap_usb_config {
+
+ unsigned register_host:1;
+ unsigned register_dev:1;
+ u8 otg;
+
+ u8 hmc_mode;
+
+ u8 rwc;
+
+ u8 pins[3];
+};
+
+struct omap_lcd_config {
+ char panel_name[16];
+ char ctrl_name[16];
+ s16 nreset_gpio;
+ u8 data_lines;
+};
+
+struct device;
+struct fb_info;
+struct omap_backlight_config {
+ int default_intensity;
+ int (*set_power)(struct device *dev, int state);
+ int (*check_fb)(struct fb_info *fb);
+};
+
+struct omap_fbmem_config {
+ u32 start;
+ u32 size;
+};
+
+struct omap_pwm_led_platform_data {
+ const char *name;
+ int intensity_timer;
+ int blink_timer;
+ void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off);
+};
+
+struct omap_gpio_switch_config {
+ char name[12];
+ u16 gpio;
+ int flags:4;
+ int type:4;
+ int key_code:24;
+};
+
+struct omap_uart_config {
+
+ unsigned int enabled_uarts;
+};
+
+struct omap_flash_part_config {
+ char part_table[0];
+};
+
+struct omap_boot_reason_config {
+ char reason_str[12];
+};
+
+struct omap_version_config {
+ char component[12];
+ char version[12];
+};
+
+struct omap_board_config_entry {
+ u16 tag;
+ u16 len;
+ u8 data[0];
+};
+
+struct omap_board_config_kernel {
+ u16 tag;
+ const void *data;
+};
+
+struct omap_bluetooth_config {
+ u8 chip_type;
+ u8 bt_uart;
+ u8 bd_addr[6];
+ u8 bt_sysclk;
+ int bt_wakeup_gpio;
+ int host_wakeup_gpio;
+ int reset_gpio;
+};
+
+#define omap_get_config(tag, type)   ((const type *) __omap_get_config((tag), sizeof(type), 0))
+#define omap_get_nr_config(tag, type, nr)   ((const type *) __omap_get_config((tag), sizeof(type), (nr)))
+
+#endif
diff --git a/libc/kernel/arch-arm/asm/arch/cpu.h b/libc/kernel/arch-arm/asm/arch/cpu.h
new file mode 100644
index 0000000..fa7a408
--- /dev/null
+++ b/libc/kernel/arch-arm/asm/arch/cpu.h
@@ -0,0 +1,57 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef __ASM_ARCH_OMAP_CPU_H
+#define __ASM_ARCH_OMAP_CPU_H
+
+#define omap2_cpu_rev() ((system_rev >> 8) & 0x0f)
+
+#undef MULTI_OMAP1
+#undef MULTI_OMAP2
+#undef OMAP_NAME
+
+#define GET_OMAP_CLASS (system_rev & 0xff)
+
+#define IS_OMAP_CLASS(class, id)  static inline int is_omap ##class (void)  {   return (GET_OMAP_CLASS == (id)) ? 1 : 0;  }
+
+#define GET_OMAP_SUBCLASS ((system_rev >> 20) & 0x0fff)
+
+#define IS_OMAP_SUBCLASS(subclass, id)  static inline int is_omap ##subclass (void)  {   return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0;  }
+
+#define cpu_is_omap7xx() 0
+#define cpu_is_omap15xx() 0
+#define cpu_is_omap16xx() 0
+#define cpu_is_omap24xx() 0
+#define cpu_is_omap242x() 0
+#define cpu_is_omap243x() 0
+#ifdef MULTI_OMAP1
+#else
+#endif
+#define GET_OMAP_TYPE ((system_rev >> 16) & 0xffff)
+#define IS_OMAP_TYPE(type, id)  static inline int is_omap ##type (void)  {   return (GET_OMAP_TYPE == (id)) ? 1 : 0;  }
+#define cpu_is_omap310() 0
+#define cpu_is_omap730() 0
+#define cpu_is_omap1510() 0
+#define cpu_is_omap1610() 0
+#define cpu_is_omap5912() 0
+#define cpu_is_omap1611() 0
+#define cpu_is_omap1621() 0
+#define cpu_is_omap1710() 0
+#define cpu_is_omap2420() 0
+#define cpu_is_omap2422() 0
+#define cpu_is_omap2423() 0
+#define cpu_is_omap2430() 0
+#ifdef MULTI_OMAP1
+#else
+#endif
+#define cpu_class_is_omap1() (cpu_is_omap730() || cpu_is_omap15xx() ||   cpu_is_omap16xx())
+#define cpu_class_is_omap2() cpu_is_omap24xx()
+#endif
diff --git a/libc/kernel/arch-arm/asm/arch/dma.h b/libc/kernel/arch-arm/asm/arch/dma.h
new file mode 100644
index 0000000..5e5be76
--- /dev/null
+++ b/libc/kernel/arch-arm/asm/arch/dma.h
@@ -0,0 +1,318 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#define OMAP_DMA_BASE (0xfffed800)
+#define OMAP_DMA_GCR (OMAP_DMA_BASE + 0x400)
+#define OMAP_DMA_GSCR (OMAP_DMA_BASE + 0x404)
+#define OMAP_DMA_GRST (OMAP_DMA_BASE + 0x408)
+#define OMAP_DMA_HW_ID (OMAP_DMA_BASE + 0x442)
+#define OMAP_DMA_PCH2_ID (OMAP_DMA_BASE + 0x444)
+#define OMAP_DMA_PCH0_ID (OMAP_DMA_BASE + 0x446)
+#define OMAP_DMA_PCH1_ID (OMAP_DMA_BASE + 0x448)
+#define OMAP_DMA_PCHG_ID (OMAP_DMA_BASE + 0x44a)
+#define OMAP_DMA_PCHD_ID (OMAP_DMA_BASE + 0x44c)
+#define OMAP_DMA_CAPS_0_U (OMAP_DMA_BASE + 0x44e)
+#define OMAP_DMA_CAPS_0_L (OMAP_DMA_BASE + 0x450)
+#define OMAP_DMA_CAPS_1_U (OMAP_DMA_BASE + 0x452)
+#define OMAP_DMA_CAPS_1_L (OMAP_DMA_BASE + 0x454)
+#define OMAP_DMA_CAPS_2 (OMAP_DMA_BASE + 0x456)
+#define OMAP_DMA_CAPS_3 (OMAP_DMA_BASE + 0x458)
+#define OMAP_DMA_CAPS_4 (OMAP_DMA_BASE + 0x45a)
+#define OMAP_DMA_PCH2_SR (OMAP_DMA_BASE + 0x460)
+#define OMAP_DMA_PCH0_SR (OMAP_DMA_BASE + 0x480)
+#define OMAP_DMA_PCH1_SR (OMAP_DMA_BASE + 0x482)
+#define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0)
+
+#define OMAP24XX_DMA_BASE (L4_24XX_BASE + 0x56000)
+#define OMAP_DMA4_REVISION (OMAP24XX_DMA_BASE + 0x00)
+#define OMAP_DMA4_GCR_REG (OMAP24XX_DMA_BASE + 0x78)
+#define OMAP_DMA4_IRQSTATUS_L0 (OMAP24XX_DMA_BASE + 0x08)
+#define OMAP_DMA4_IRQSTATUS_L1 (OMAP24XX_DMA_BASE + 0x0c)
+#define OMAP_DMA4_IRQSTATUS_L2 (OMAP24XX_DMA_BASE + 0x10)
+#define OMAP_DMA4_IRQSTATUS_L3 (OMAP24XX_DMA_BASE + 0x14)
+#define OMAP_DMA4_IRQENABLE_L0 (OMAP24XX_DMA_BASE + 0x18)
+#define OMAP_DMA4_IRQENABLE_L1 (OMAP24XX_DMA_BASE + 0x1c)
+#define OMAP_DMA4_IRQENABLE_L2 (OMAP24XX_DMA_BASE + 0x20)
+#define OMAP_DMA4_IRQENABLE_L3 (OMAP24XX_DMA_BASE + 0x24)
+#define OMAP_DMA4_SYSSTATUS (OMAP24XX_DMA_BASE + 0x28)
+#define OMAP_DMA4_CAPS_0 (OMAP24XX_DMA_BASE + 0x64)
+#define OMAP_DMA4_CAPS_2 (OMAP24XX_DMA_BASE + 0x6c)
+#define OMAP_DMA4_CAPS_3 (OMAP24XX_DMA_BASE + 0x70)
+#define OMAP_DMA4_CAPS_4 (OMAP24XX_DMA_BASE + 0x74)
+
+#define OMAP_LOGICAL_DMA_CH_COUNT 32  
+
+#define OMAP_DMA_CCR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x80)
+#define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x84)
+#define OMAP_DMA_CICR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x88)
+#define OMAP_DMA_CSR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x8c)
+#define OMAP_DMA_CSDP_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x90)
+#define OMAP_DMA_CEN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x94)
+#define OMAP_DMA_CFN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x98)
+#define OMAP_DMA_CSEI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa4)
+#define OMAP_DMA_CSFI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa8)
+#define OMAP_DMA_CDEI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xac)
+#define OMAP_DMA_CDFI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb0)
+#define OMAP_DMA_CSAC_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb4)
+#define OMAP_DMA_CDAC_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb8)
+
+#define OMAP1_DMA_CSSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x08)
+#define OMAP1_DMA_CSSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0a)
+#define OMAP1_DMA_CDSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0c)
+#define OMAP1_DMA_CDSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0e)
+#define OMAP1_DMA_COLOR_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x20)
+#define OMAP1_DMA_CCR2_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x24)
+#define OMAP1_DMA_COLOR_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x22)
+#define OMAP1_DMA_LCH_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
+
+#define OMAP2_DMA_CSSA_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x9c)
+#define OMAP2_DMA_CDSA_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa0)
+#define OMAP2_DMA_CCEN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xbc)
+#define OMAP2_DMA_CCFN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc0)
+#define OMAP2_DMA_COLOR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc4)
+
+#define OMAP_DMA_NO_DEVICE 0
+#define OMAP_DMA_MCSI1_TX 1
+#define OMAP_DMA_MCSI1_RX 2
+#define OMAP_DMA_I2C_RX 3
+#define OMAP_DMA_I2C_TX 4
+#define OMAP_DMA_EXT_NDMA_REQ 5
+#define OMAP_DMA_EXT_NDMA_REQ2 6
+#define OMAP_DMA_UWIRE_TX 7
+#define OMAP_DMA_MCBSP1_TX 8
+#define OMAP_DMA_MCBSP1_RX 9
+#define OMAP_DMA_MCBSP3_TX 10
+#define OMAP_DMA_MCBSP3_RX 11
+#define OMAP_DMA_UART1_TX 12
+#define OMAP_DMA_UART1_RX 13
+#define OMAP_DMA_UART2_TX 14
+#define OMAP_DMA_UART2_RX 15
+#define OMAP_DMA_MCBSP2_TX 16
+#define OMAP_DMA_MCBSP2_RX 17
+#define OMAP_DMA_UART3_TX 18
+#define OMAP_DMA_UART3_RX 19
+#define OMAP_DMA_CAMERA_IF_RX 20
+#define OMAP_DMA_MMC_TX 21
+#define OMAP_DMA_MMC_RX 22
+#define OMAP_DMA_NAND 23
+#define OMAP_DMA_IRQ_LCD_LINE 24
+#define OMAP_DMA_MEMORY_STICK 25
+#define OMAP_DMA_USB_W2FC_RX0 26
+#define OMAP_DMA_USB_W2FC_RX1 27
+#define OMAP_DMA_USB_W2FC_RX2 28
+#define OMAP_DMA_USB_W2FC_TX0 29
+#define OMAP_DMA_USB_W2FC_TX1 30
+#define OMAP_DMA_USB_W2FC_TX2 31
+
+#define OMAP_DMA_CRYPTO_DES_IN 32
+#define OMAP_DMA_SPI_TX 33
+#define OMAP_DMA_SPI_RX 34
+#define OMAP_DMA_CRYPTO_HASH 35
+#define OMAP_DMA_CCP_ATTN 36
+#define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
+#define OMAP_DMA_CMT_APE_TX_CHAN_0 38
+#define OMAP_DMA_CMT_APE_RV_CHAN_0 39
+#define OMAP_DMA_CMT_APE_TX_CHAN_1 40
+#define OMAP_DMA_CMT_APE_RV_CHAN_1 41
+#define OMAP_DMA_CMT_APE_TX_CHAN_2 42
+#define OMAP_DMA_CMT_APE_RV_CHAN_2 43
+#define OMAP_DMA_CMT_APE_TX_CHAN_3 44
+#define OMAP_DMA_CMT_APE_RV_CHAN_3 45
+#define OMAP_DMA_CMT_APE_TX_CHAN_4 46
+#define OMAP_DMA_CMT_APE_RV_CHAN_4 47
+#define OMAP_DMA_CMT_APE_TX_CHAN_5 48
+#define OMAP_DMA_CMT_APE_RV_CHAN_5 49
+#define OMAP_DMA_CMT_APE_TX_CHAN_6 50
+#define OMAP_DMA_CMT_APE_RV_CHAN_6 51
+#define OMAP_DMA_CMT_APE_TX_CHAN_7 52
+#define OMAP_DMA_CMT_APE_RV_CHAN_7 53
+#define OMAP_DMA_MMC2_TX 54
+#define OMAP_DMA_MMC2_RX 55
+#define OMAP_DMA_CRYPTO_DES_OUT 56
+
+#define OMAP24XX_DMA_NO_DEVICE 0
+#define OMAP24XX_DMA_XTI_DMA 1  
+#define OMAP24XX_DMA_EXT_DMAREQ0 2  
+#define OMAP24XX_DMA_EXT_DMAREQ1 3  
+#define OMAP24XX_DMA_GPMC 4  
+#define OMAP24XX_DMA_GFX 5  
+#define OMAP24XX_DMA_DSS 6  
+#define OMAP24XX_DMA_VLYNQ_TX 7  
+#define OMAP24XX_DMA_CWT 8  
+#define OMAP24XX_DMA_AES_TX 9  
+#define OMAP24XX_DMA_AES_RX 10  
+#define OMAP24XX_DMA_DES_TX 11  
+#define OMAP24XX_DMA_DES_RX 12  
+#define OMAP24XX_DMA_SHA1MD5_RX 13  
+#define OMAP24XX_DMA_EXT_DMAREQ2 14  
+#define OMAP24XX_DMA_EXT_DMAREQ3 15  
+#define OMAP24XX_DMA_EXT_DMAREQ4 16  
+#define OMAP24XX_DMA_EAC_AC_RD 17  
+#define OMAP24XX_DMA_EAC_AC_WR 18  
+#define OMAP24XX_DMA_EAC_MD_UL_RD 19  
+#define OMAP24XX_DMA_EAC_MD_UL_WR 20  
+#define OMAP24XX_DMA_EAC_MD_DL_RD 21  
+#define OMAP24XX_DMA_EAC_MD_DL_WR 22  
+#define OMAP24XX_DMA_EAC_BT_UL_RD 23  
+#define OMAP24XX_DMA_EAC_BT_UL_WR 24  
+#define OMAP24XX_DMA_EAC_BT_DL_RD 25  
+#define OMAP24XX_DMA_EAC_BT_DL_WR 26  
+#define OMAP24XX_DMA_I2C1_TX 27  
+#define OMAP24XX_DMA_I2C1_RX 28  
+#define OMAP24XX_DMA_I2C2_TX 29  
+#define OMAP24XX_DMA_I2C2_RX 30  
+#define OMAP24XX_DMA_MCBSP1_TX 31  
+#define OMAP24XX_DMA_MCBSP1_RX 32  
+#define OMAP24XX_DMA_MCBSP2_TX 33  
+#define OMAP24XX_DMA_MCBSP2_RX 34  
+#define OMAP24XX_DMA_SPI1_TX0 35  
+#define OMAP24XX_DMA_SPI1_RX0 36  
+#define OMAP24XX_DMA_SPI1_TX1 37  
+#define OMAP24XX_DMA_SPI1_RX1 38  
+#define OMAP24XX_DMA_SPI1_TX2 39  
+#define OMAP24XX_DMA_SPI1_RX2 40  
+#define OMAP24XX_DMA_SPI1_TX3 41  
+#define OMAP24XX_DMA_SPI1_RX3 42  
+#define OMAP24XX_DMA_SPI2_TX0 43  
+#define OMAP24XX_DMA_SPI2_RX0 44  
+#define OMAP24XX_DMA_SPI2_TX1 45  
+#define OMAP24XX_DMA_SPI2_RX1 46  
+
+#define OMAP24XX_DMA_UART1_TX 49  
+#define OMAP24XX_DMA_UART1_RX 50  
+#define OMAP24XX_DMA_UART2_TX 51  
+#define OMAP24XX_DMA_UART2_RX 52  
+#define OMAP24XX_DMA_UART3_TX 53  
+#define OMAP24XX_DMA_UART3_RX 54  
+#define OMAP24XX_DMA_USB_W2FC_TX0 55  
+#define OMAP24XX_DMA_USB_W2FC_RX0 56  
+#define OMAP24XX_DMA_USB_W2FC_TX1 57  
+#define OMAP24XX_DMA_USB_W2FC_RX1 58  
+#define OMAP24XX_DMA_USB_W2FC_TX2 59  
+#define OMAP24XX_DMA_USB_W2FC_RX2 60  
+#define OMAP24XX_DMA_MMC1_TX 61  
+#define OMAP24XX_DMA_MMC1_RX 62  
+#define OMAP24XX_DMA_MS 63  
+#define OMAP24XX_DMA_EXT_DMAREQ5 64  
+
+#define OMAP1510_DMA_LCD_BASE (0xfffedb00)
+#define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00)
+#define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02)
+#define OMAP1510_DMA_LCD_TOP_F1_U (OMAP1510_DMA_LCD_BASE + 0x04)
+#define OMAP1510_DMA_LCD_BOT_F1_L (OMAP1510_DMA_LCD_BASE + 0x06)
+#define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08)
+
+#define OMAP1610_DMA_LCD_BASE (0xfffee300)
+#define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0)
+#define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2)
+#define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4)
+#define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8)
+#define OMAP1610_DMA_LCD_TOP_B1_U (OMAP1610_DMA_LCD_BASE + 0xca)
+#define OMAP1610_DMA_LCD_BOT_B1_L (OMAP1610_DMA_LCD_BASE + 0xcc)
+#define OMAP1610_DMA_LCD_BOT_B1_U (OMAP1610_DMA_LCD_BASE + 0xce)
+#define OMAP1610_DMA_LCD_TOP_B2_L (OMAP1610_DMA_LCD_BASE + 0xd0)
+#define OMAP1610_DMA_LCD_TOP_B2_U (OMAP1610_DMA_LCD_BASE + 0xd2)
+#define OMAP1610_DMA_LCD_BOT_B2_L (OMAP1610_DMA_LCD_BASE + 0xd4)
+#define OMAP1610_DMA_LCD_BOT_B2_U (OMAP1610_DMA_LCD_BASE + 0xd6)
+#define OMAP1610_DMA_LCD_SRC_EI_B1 (OMAP1610_DMA_LCD_BASE + 0xd8)
+#define OMAP1610_DMA_LCD_SRC_FI_B1_L (OMAP1610_DMA_LCD_BASE + 0xda)
+#define OMAP1610_DMA_LCD_SRC_EN_B1 (OMAP1610_DMA_LCD_BASE + 0xe0)
+#define OMAP1610_DMA_LCD_SRC_FN_B1 (OMAP1610_DMA_LCD_BASE + 0xe4)
+#define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea)
+#define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4)
+
+#define OMAP1_DMA_TOUT_IRQ (1 << 0)
+#define OMAP_DMA_DROP_IRQ (1 << 1)
+#define OMAP_DMA_HALF_IRQ (1 << 2)
+#define OMAP_DMA_FRAME_IRQ (1 << 3)
+#define OMAP_DMA_LAST_IRQ (1 << 4)
+#define OMAP_DMA_BLOCK_IRQ (1 << 5)
+#define OMAP1_DMA_SYNC_IRQ (1 << 6)
+#define OMAP2_DMA_PKT_IRQ (1 << 7)
+#define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8)
+#define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9)
+#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10)
+#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
+
+#define OMAP_DMA_DATA_TYPE_S8 0x00
+#define OMAP_DMA_DATA_TYPE_S16 0x01
+#define OMAP_DMA_DATA_TYPE_S32 0x02
+
+#define OMAP_DMA_SYNC_ELEMENT 0x00
+#define OMAP_DMA_SYNC_FRAME 0x01
+#define OMAP_DMA_SYNC_BLOCK 0x02
+
+#define OMAP_DMA_PORT_EMIFF 0x00
+#define OMAP_DMA_PORT_EMIFS 0x01
+#define OMAP_DMA_PORT_OCP_T1 0x02
+#define OMAP_DMA_PORT_TIPB 0x03
+#define OMAP_DMA_PORT_OCP_T2 0x04
+#define OMAP_DMA_PORT_MPUI 0x05
+
+#define OMAP_DMA_AMODE_CONSTANT 0x00
+#define OMAP_DMA_AMODE_POST_INC 0x01
+#define OMAP_DMA_AMODE_SINGLE_IDX 0x02
+#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03
+
+enum {
+ OMAP_LCD_DMA_B1_TOP,
+ OMAP_LCD_DMA_B1_BOTTOM,
+ OMAP_LCD_DMA_B2_TOP,
+ OMAP_LCD_DMA_B2_BOTTOM
+};
+
+enum omap_dma_burst_mode {
+ OMAP_DMA_DATA_BURST_DIS = 0,
+ OMAP_DMA_DATA_BURST_4,
+ OMAP_DMA_DATA_BURST_8,
+ OMAP_DMA_DATA_BURST_16,
+};
+
+enum omap_dma_color_mode {
+ OMAP_DMA_COLOR_DIS = 0,
+ OMAP_DMA_CONSTANT_FILL,
+ OMAP_DMA_TRANSPARENT_COPY
+};
+
+enum omap_dma_write_mode {
+ OMAP_DMA_WRITE_NON_POSTED = 0,
+ OMAP_DMA_WRITE_POSTED,
+ OMAP_DMA_WRITE_LAST_NON_POSTED
+};
+
+struct omap_dma_channel_params {
+ int data_type;
+ int elem_count;
+ int frame_count;
+
+ int src_port;
+ int src_amode;
+ unsigned long src_start;
+ int src_ei;
+ int src_fi;
+
+ int dst_port;
+ int dst_amode;
+ unsigned long dst_start;
+ int dst_ei;
+ int dst_fi;
+
+ int trigger;
+ int sync_mode;
+ int src_or_dst_synch;
+
+ int ie;
+};
+
+#endif
diff --git a/libc/kernel/arch-arm/asm/arch/fpga.h b/libc/kernel/arch-arm/asm/arch/fpga.h
new file mode 100644
index 0000000..a1b210d
--- /dev/null
+++ b/libc/kernel/arch-arm/asm/arch/fpga.h
@@ -0,0 +1,160 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef __ASM_ARCH_OMAP_FPGA_H
+#define __ASM_ARCH_OMAP_FPGA_H
+
+#define omap1510_fpga_init_irq() (0)
+
+#define fpga_read(reg) __raw_readb(reg)
+#define fpga_write(val, reg) __raw_writeb(val, reg)
+
+#define H2P2_DBG_FPGA_BASE 0xE8000000  
+#define H2P2_DBG_FPGA_SIZE SZ_4K  
+#define H2P2_DBG_FPGA_START 0x04000000  
+
+#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300)
+#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10)  
+#define H2P2_DBG_FPGA_BOARD_REV (H2P2_DBG_FPGA_BASE + 0x12)  
+#define H2P2_DBG_FPGA_GPIO (H2P2_DBG_FPGA_BASE + 0x14)  
+#define H2P2_DBG_FPGA_LEDS (H2P2_DBG_FPGA_BASE + 0x16)  
+#define H2P2_DBG_FPGA_MISC_INPUTS (H2P2_DBG_FPGA_BASE + 0x18)  
+#define H2P2_DBG_FPGA_LAN_STATUS (H2P2_DBG_FPGA_BASE + 0x1A)  
+#define H2P2_DBG_FPGA_LAN_RESET (H2P2_DBG_FPGA_BASE + 0x1C)  
+
+struct h2p2_dbg_fpga {
+
+ u16 smc91x[8];
+
+ u16 fpga_rev;
+ u16 board_rev;
+ u16 gpio_outputs;
+ u16 leds;
+
+ u16 misc_inputs;
+ u16 lan_status;
+ u16 lan_reset;
+ u16 reserved0;
+
+ u16 ps2_data;
+ u16 ps2_ctrl;
+
+};
+
+#define H2P2_DBG_FPGA_LED_GREEN (1 << 15)
+#define H2P2_DBG_FPGA_LED_AMBER (1 << 14)
+#define H2P2_DBG_FPGA_LED_RED (1 << 13)
+#define H2P2_DBG_FPGA_LED_BLUE (1 << 12)
+
+#define H2P2_DBG_FPGA_LOAD_METER (1 << 0) 
+#define H2P2_DBG_FPGA_LOAD_METER_SIZE 11
+#define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
+
+#define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0)
+#define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1)
+
+#define OMAP1510_FPGA_BASE 0xE8000000  
+#define OMAP1510_FPGA_SIZE SZ_4K
+#define OMAP1510_FPGA_START 0x08000000  
+
+#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0)
+#define OMAP1510_FPGA_REV_HIGH (OMAP1510_FPGA_BASE + 0x1)
+
+#define OMAP1510_FPGA_LCD_PANEL_CONTROL (OMAP1510_FPGA_BASE + 0x2)
+#define OMAP1510_FPGA_LED_DIGIT (OMAP1510_FPGA_BASE + 0x3)
+#define INNOVATOR_FPGA_HID_SPI (OMAP1510_FPGA_BASE + 0x4)
+#define OMAP1510_FPGA_POWER (OMAP1510_FPGA_BASE + 0x5)
+
+#define OMAP1510_FPGA_ISR_LO (OMAP1510_FPGA_BASE + 0x6)
+#define OMAP1510_FPGA_ISR_HI (OMAP1510_FPGA_BASE + 0x7)
+
+#define OMAP1510_FPGA_IMR_LO (OMAP1510_FPGA_BASE + 0x8)
+#define OMAP1510_FPGA_IMR_HI (OMAP1510_FPGA_BASE + 0x9)
+
+#define OMAP1510_FPGA_HOST_RESET (OMAP1510_FPGA_BASE + 0xa)
+#define OMAP1510_FPGA_RST (OMAP1510_FPGA_BASE + 0xb)
+
+#define OMAP1510_FPGA_AUDIO (OMAP1510_FPGA_BASE + 0xc)
+#define OMAP1510_FPGA_DIP (OMAP1510_FPGA_BASE + 0xe)
+#define OMAP1510_FPGA_FPGA_IO (OMAP1510_FPGA_BASE + 0xf)
+#define OMAP1510_FPGA_UART1 (OMAP1510_FPGA_BASE + 0x14)
+#define OMAP1510_FPGA_UART2 (OMAP1510_FPGA_BASE + 0x15)
+#define OMAP1510_FPGA_OMAP1510_STATUS (OMAP1510_FPGA_BASE + 0x16)
+#define OMAP1510_FPGA_BOARD_REV (OMAP1510_FPGA_BASE + 0x18)
+#define OMAP1510P1_PPT_DATA (OMAP1510_FPGA_BASE + 0x100)
+#define OMAP1510P1_PPT_STATUS (OMAP1510_FPGA_BASE + 0x101)
+#define OMAP1510P1_PPT_CONTROL (OMAP1510_FPGA_BASE + 0x102)
+
+#define OMAP1510_FPGA_TOUCHSCREEN (OMAP1510_FPGA_BASE + 0x204)
+
+#define INNOVATOR_FPGA_INFO (OMAP1510_FPGA_BASE + 0x205)
+#define INNOVATOR_FPGA_LCD_BRIGHT_LO (OMAP1510_FPGA_BASE + 0x206)
+#define INNOVATOR_FPGA_LCD_BRIGHT_HI (OMAP1510_FPGA_BASE + 0x207)
+#define INNOVATOR_FPGA_LED_GRN_LO (OMAP1510_FPGA_BASE + 0x208)
+#define INNOVATOR_FPGA_LED_GRN_HI (OMAP1510_FPGA_BASE + 0x209)
+#define INNOVATOR_FPGA_LED_RED_LO (OMAP1510_FPGA_BASE + 0x20a)
+#define INNOVATOR_FPGA_LED_RED_HI (OMAP1510_FPGA_BASE + 0x20b)
+#define INNOVATOR_FPGA_CAM_USB_CONTROL (OMAP1510_FPGA_BASE + 0x20c)
+#define INNOVATOR_FPGA_EXP_CONTROL (OMAP1510_FPGA_BASE + 0x20d)
+#define INNOVATOR_FPGA_ISR2 (OMAP1510_FPGA_BASE + 0x20e)
+#define INNOVATOR_FPGA_IMR2 (OMAP1510_FPGA_BASE + 0x210)
+
+#define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300)
+
+#define OMAP1510_FPGA_RESET_VALUE 0x42
+
+#define OMAP1510_FPGA_PCR_IF_PD0 (1 << 7)
+#define OMAP1510_FPGA_PCR_COM2_EN (1 << 6)
+#define OMAP1510_FPGA_PCR_COM1_EN (1 << 5)
+#define OMAP1510_FPGA_PCR_EXP_PD0 (1 << 4)
+#define OMAP1510_FPGA_PCR_EXP_PD1 (1 << 3)
+#define OMAP1510_FPGA_PCR_48MHZ_CLK (1 << 2)
+#define OMAP1510_FPGA_PCR_4MHZ_CLK (1 << 1)
+#define OMAP1510_FPGA_PCR_RSRVD_BIT0 (1 << 0)
+
+#define OMAP1510_FPGA_HID_SCLK (1<<0)  
+#define OMAP1510_FPGA_HID_MOSI (1<<1)  
+#define OMAP1510_FPGA_HID_nSS (1<<2)  
+#define OMAP1510_FPGA_HID_nHSUS (1<<3)  
+#define OMAP1510_FPGA_HID_MISO (1<<4)  
+#define OMAP1510_FPGA_HID_ATN (1<<5)  
+#define OMAP1510_FPGA_HID_rsrvd (1<<6)
+#define OMAP1510_FPGA_HID_RESETn (1<<7)  
+
+#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13)
+
+#define OMAP1510_IH_FPGA_BASE IH_BOARD_BASE
+#define OMAP1510_INT_FPGA_ATN (OMAP1510_IH_FPGA_BASE + 0)
+#define OMAP1510_INT_FPGA_ACK (OMAP1510_IH_FPGA_BASE + 1)
+#define OMAP1510_INT_FPGA2 (OMAP1510_IH_FPGA_BASE + 2)
+#define OMAP1510_INT_FPGA3 (OMAP1510_IH_FPGA_BASE + 3)
+#define OMAP1510_INT_FPGA4 (OMAP1510_IH_FPGA_BASE + 4)
+#define OMAP1510_INT_FPGA5 (OMAP1510_IH_FPGA_BASE + 5)
+#define OMAP1510_INT_FPGA6 (OMAP1510_IH_FPGA_BASE + 6)
+#define OMAP1510_INT_FPGA7 (OMAP1510_IH_FPGA_BASE + 7)
+#define OMAP1510_INT_FPGA8 (OMAP1510_IH_FPGA_BASE + 8)
+#define OMAP1510_INT_FPGA9 (OMAP1510_IH_FPGA_BASE + 9)
+#define OMAP1510_INT_FPGA10 (OMAP1510_IH_FPGA_BASE + 10)
+#define OMAP1510_INT_FPGA11 (OMAP1510_IH_FPGA_BASE + 11)
+#define OMAP1510_INT_FPGA12 (OMAP1510_IH_FPGA_BASE + 12)
+#define OMAP1510_INT_ETHER (OMAP1510_IH_FPGA_BASE + 13)
+#define OMAP1510_INT_FPGAUART1 (OMAP1510_IH_FPGA_BASE + 14)
+#define OMAP1510_INT_FPGAUART2 (OMAP1510_IH_FPGA_BASE + 15)
+#define OMAP1510_INT_FPGA_TS (OMAP1510_IH_FPGA_BASE + 16)
+#define OMAP1510_INT_FPGA17 (OMAP1510_IH_FPGA_BASE + 17)
+#define OMAP1510_INT_FPGA_CAM (OMAP1510_IH_FPGA_BASE + 18)
+#define OMAP1510_INT_FPGA_RTC_A (OMAP1510_IH_FPGA_BASE + 19)
+#define OMAP1510_INT_FPGA_RTC_B (OMAP1510_IH_FPGA_BASE + 20)
+#define OMAP1510_INT_FPGA_CD (OMAP1510_IH_FPGA_BASE + 21)
+#define OMAP1510_INT_FPGA22 (OMAP1510_IH_FPGA_BASE + 22)
+#define OMAP1510_INT_FPGA23 (OMAP1510_IH_FPGA_BASE + 23)
+
+#endif
diff --git a/libc/kernel/arch-arm/asm/arch/gpio-switch.h b/libc/kernel/arch-arm/asm/arch/gpio-switch.h
new file mode 100644
index 0000000..20ea3f2
--- /dev/null
+++ b/libc/kernel/arch-arm/asm/arch/gpio-switch.h
@@ -0,0 +1,37 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef __ASM_ARCH_OMAP_GPIO_SWITCH_H
+#define __ASM_ARCH_OMAP_GPIO_SWITCH_H
+
+#include <linux/types.h>
+
+#define OMAP_GPIO_SWITCH_TYPE_COVER 0x0000
+#define OMAP_GPIO_SWITCH_TYPE_CONNECTION 0x0001
+#define OMAP_GPIO_SWITCH_TYPE_ACTIVITY 0x0002
+#define OMAP_GPIO_SWITCH_FLAG_INVERTED 0x0001
+#define OMAP_GPIO_SWITCH_FLAG_OUTPUT 0x0002
+
+struct omap_gpio_switch {
+ const char *name;
+ s16 gpio;
+ unsigned flags:4;
+ unsigned type:4;
+
+ u16 debounce_rising;
+
+ u16 debounce_falling;
+
+ void (* notify)(void *data, int state);
+ void *notify_data;
+};
+
+#endif
diff --git a/libc/kernel/arch-arm/asm/arch/gpio.h b/libc/kernel/arch-arm/asm/arch/gpio.h
new file mode 100644
index 0000000..332246d
--- /dev/null
+++ b/libc/kernel/arch-arm/asm/arch/gpio.h
@@ -0,0 +1,49 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef __ASM_ARCH_OMAP_GPIO_H
+#define __ASM_ARCH_OMAP_GPIO_H
+
+#include <asm/hardware.h>
+#include <asm/arch/irqs.h>
+#include <asm/io.h>
+
+#define OMAP_MPUIO_BASE (void __iomem *)0xfffb5000
+
+#define OMAP_MPUIO_INPUT_LATCH 0x00
+#define OMAP_MPUIO_OUTPUT 0x04
+#define OMAP_MPUIO_IO_CNTL 0x08
+#define OMAP_MPUIO_KBR_LATCH 0x10
+#define OMAP_MPUIO_KBC 0x14
+#define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
+#define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
+#define OMAP_MPUIO_KBD_INT 0x20
+#define OMAP_MPUIO_GPIO_INT 0x24
+#define OMAP_MPUIO_KBD_MASKIT 0x28
+#define OMAP_MPUIO_GPIO_MASKIT 0x2c
+#define OMAP_MPUIO_GPIO_DEBOUNCING 0x30
+#define OMAP_MPUIO_LATCH 0x34
+
+#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr))
+#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES)
+
+#define OMAP_GPIO_IRQ(nr) (OMAP_GPIO_IS_MPUIO(nr) ?   IH_MPUIO_BASE + ((nr) & 0x0f) :   IH_GPIO_BASE + (nr))
+
+struct omap_machine_gpio_bank {
+ int start;
+ int end;
+
+ void (*set_gpio_direction)(int gpio, int is_input);
+ void (*set_gpio_dataout)(int gpio, int enable);
+ int (*get_gpio_datain)(int gpio);
+};
+
+#endif
diff --git a/libc/kernel/arch-arm/asm/arch/hardware.h b/libc/kernel/arch-arm/asm/arch/hardware.h
new file mode 100644
index 0000000..e515ee8
--- /dev/null
+++ b/libc/kernel/arch-arm/asm/arch/hardware.h
@@ -0,0 +1,157 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef __ASM_ARCH_OMAP_HARDWARE_H
+#define __ASM_ARCH_OMAP_HARDWARE_H
+
+#include <asm/sizes.h>
+#ifndef __ASSEMBLER__
+#include <asm/types.h>
+#include <asm/arch/cpu.h>
+#endif
+#include <asm/arch/io.h>
+#include <asm/arch/serial.h>
+
+#define OMAP_MPU_TIMER1_BASE (0xfffec500)
+#define OMAP_MPU_TIMER2_BASE (0xfffec600)
+#define OMAP_MPU_TIMER3_BASE (0xfffec700)
+#define MPU_TIMER_FREE (1 << 6)
+#define MPU_TIMER_CLOCK_ENABLE (1 << 5)
+#define MPU_TIMER_AR (1 << 1)
+#define MPU_TIMER_ST (1 << 0)
+
+#define CLKGEN_REG_BASE (0xfffece00)
+#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
+#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
+#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
+#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
+#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
+#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
+#define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
+#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
+
+#define CK_RATEF 1
+#define CK_IDLEF 2
+#define CK_ENABLEF 4
+#define CK_SELECTF 8
+#define SETARM_IDLE_SHIFT
+
+#define DPLL_CTL (0xfffecf00)
+
+#define DSP_CONFIG_REG_BASE (0xe1008000)
+#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
+#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
+#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
+#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14)
+
+#define ULPD_REG_BASE (0xfffe0800)
+#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
+#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
+#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
+#define DIS_USB_PVCI_CLK (1 << 5)  
+#define USB_MCLK_EN (1 << 4)  
+#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
+#define SOFT_UDC_REQ (1 << 4)
+#define SOFT_USB_CLK_REQ (1 << 3)
+#define SOFT_DPLL_REQ (1 << 0)
+#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)
+#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)
+#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)
+#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)
+#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68)
+#define DIS_MMC2_DPLL_REQ (1 << 11)
+#define DIS_MMC1_DPLL_REQ (1 << 10)
+#define DIS_UART3_DPLL_REQ (1 << 9)
+#define DIS_UART2_DPLL_REQ (1 << 8)
+#define DIS_UART1_DPLL_REQ (1 << 7)
+#define DIS_USB_HOST_DPLL_REQ (1 << 6)
+#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74)
+#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)
+
+#define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
+#define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)
+#define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
+#define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
+#define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8)
+
+#define MOD_CONF_CTRL_0 0xfffe1080
+#define MOD_CONF_CTRL_1 0xfffe1110
+
+#define FUNC_MUX_CTRL_0 0xfffe1000
+#define FUNC_MUX_CTRL_1 0xfffe1004
+#define FUNC_MUX_CTRL_2 0xfffe1008
+#define COMP_MODE_CTRL_0 0xfffe100c
+#define FUNC_MUX_CTRL_3 0xfffe1010
+#define FUNC_MUX_CTRL_4 0xfffe1014
+#define FUNC_MUX_CTRL_5 0xfffe1018
+#define FUNC_MUX_CTRL_6 0xfffe101C
+#define FUNC_MUX_CTRL_7 0xfffe1020
+#define FUNC_MUX_CTRL_8 0xfffe1024
+#define FUNC_MUX_CTRL_9 0xfffe1028
+#define FUNC_MUX_CTRL_A 0xfffe102C
+#define FUNC_MUX_CTRL_B 0xfffe1030
+#define FUNC_MUX_CTRL_C 0xfffe1034
+#define FUNC_MUX_CTRL_D 0xfffe1038
+#define PULL_DWN_CTRL_0 0xfffe1040
+#define PULL_DWN_CTRL_1 0xfffe1044
+#define PULL_DWN_CTRL_2 0xfffe1048
+#define PULL_DWN_CTRL_3 0xfffe104c
+#define PULL_DWN_CTRL_4 0xfffe10ac
+
+#define FUNC_MUX_CTRL_E 0xfffe1090
+#define FUNC_MUX_CTRL_F 0xfffe1094
+#define FUNC_MUX_CTRL_10 0xfffe1098
+#define FUNC_MUX_CTRL_11 0xfffe109c
+#define FUNC_MUX_CTRL_12 0xfffe10a0
+#define PU_PD_SEL_0 0xfffe10b4
+#define PU_PD_SEL_1 0xfffe10b8
+#define PU_PD_SEL_2 0xfffe10bc
+#define PU_PD_SEL_3 0xfffe10c0
+#define PU_PD_SEL_4 0xfffe10c4
+
+#define OMAP_TIMER32K_BASE 0xFFFBC400
+
+#define TIPB_PUBLIC_CNTL_BASE 0xfffed300
+#define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8)
+#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
+#define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8)
+
+#define MPUI_BASE (0xfffec900)
+#define MPUI_CTRL (MPUI_BASE + 0x0)
+#define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4)
+#define MPUI_DEBUG_DATA (MPUI_BASE + 0x8)
+#define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc)
+#define MPUI_STATUS_REG (MPUI_BASE + 0x10)
+#define MPUI_DSP_STATUS (MPUI_BASE + 0x14)
+#define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18)
+#define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c)
+
+#define OMAP_LPG1_BASE 0xfffbd000
+#define OMAP_LPG2_BASE 0xfffbd800
+#define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00)
+#define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04)
+#define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00)
+#define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04)
+
+#define OMAP_PWL_BASE 0xfffb5800
+#define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00)
+#define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04)
+
+#include "omap730.h"
+#include "omap1510.h"
+#include "omap24xx.h"
+#include "omap16xx.h"
+
+#ifndef __ASSEMBLER__
+
+#endif
+
+#endif
diff --git a/libc/kernel/arch-arm/asm/arch/io.h b/libc/kernel/arch-arm/asm/arch/io.h
new file mode 100644
index 0000000..12ac3d4
--- /dev/null
+++ b/libc/kernel/arch-arm/asm/arch/io.h
@@ -0,0 +1,54 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#include <asm/hardware.h>
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+#define __io(a) ((void __iomem *)(PCIO_BASE + (a)))
+#define __mem_pci(a) (a)
+
+#define PCIO_BASE 0
+
+#ifndef __ASSEMBLER__
+
+#define omap_readb(a) (*(volatile unsigned char *)IO_ADDRESS(a))
+#define omap_readw(a) (*(volatile unsigned short *)IO_ADDRESS(a))
+#define omap_readl(a) (*(volatile unsigned int *)IO_ADDRESS(a))
+
+#define omap_writeb(v,a) (*(volatile unsigned char *)IO_ADDRESS(a) = (v))
+#define omap_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v))
+#define omap_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v))
+
+typedef struct { volatile u16 offset[256]; } __regbase16;
+#define __REGV16(vaddr) ((__regbase16 *)((vaddr)&~0xff))   ->offset[((vaddr)&0xff)>>1]
+#define __REG16(paddr) __REGV16(io_p2v(paddr))
+
+typedef struct { volatile u8 offset[4096]; } __regbase8;
+#define __REGV8(vaddr) ((__regbase8 *)((vaddr)&~4095))   ->offset[((vaddr)&4095)>>0]
+#define __REG8(paddr) __REGV8(io_p2v(paddr))
+
+typedef struct { volatile u32 offset[4096]; } __regbase32;
+#define __REGV32(vaddr) ((__regbase32 *)((vaddr)&~4095))   ->offset[((vaddr)&4095)>>2]
+#define __REG32(paddr) __REGV32(io_p2v(paddr))
+
+#else
+
+#define __REG8(paddr) io_p2v(paddr)
+#define __REG16(paddr) io_p2v(paddr)
+#define __REG32(paddr) io_p2v(paddr)
+
+#endif
+
+#endif
diff --git a/libc/kernel/arch-arm/asm/arch/irqs.h b/libc/kernel/arch-arm/asm/arch/irqs.h
new file mode 100644
index 0000000..3e94487
--- /dev/null
+++ b/libc/kernel/arch-arm/asm/arch/irqs.h
@@ -0,0 +1,242 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
+#define __ASM_ARCH_OMAP15XX_IRQS_H
+
+#define INT_CAMERA 1
+#define INT_FIQ 3
+#define INT_RTDX 6
+#define INT_DSP_MMU_ABORT 7
+#define INT_HOST 8
+#define INT_ABORT 9
+#define INT_DSP_MAILBOX1 10
+#define INT_DSP_MAILBOX2 11
+#define INT_BRIDGE_PRIV 13
+#define INT_GPIO_BANK1 14
+#define INT_UART3 15
+#define INT_TIMER3 16
+#define INT_DMA_CH0_6 19
+#define INT_DMA_CH1_7 20
+#define INT_DMA_CH2_8 21
+#define INT_DMA_CH3 22
+#define INT_DMA_CH4 23
+#define INT_DMA_CH5 24
+#define INT_DMA_LCD 25
+#define INT_TIMER1 26
+#define INT_WD_TIMER 27
+#define INT_BRIDGE_PUB 28
+#define INT_TIMER2 30
+#define INT_LCD_CTRL 31
+
+#define INT_1510_IH2_IRQ 0
+#define INT_1510_RES2 2
+#define INT_1510_SPI_TX 4
+#define INT_1510_SPI_RX 5
+#define INT_1510_RES12 12
+#define INT_1510_LB_MMU 17
+#define INT_1510_RES18 18
+#define INT_1510_LOCAL_BUS 29
+
+#define INT_1610_IH2_IRQ 0
+#define INT_1610_IH2_FIQ 2
+#define INT_1610_McBSP2_TX 4
+#define INT_1610_McBSP2_RX 5
+#define INT_1610_LCD_LINE 12
+#define INT_1610_GPTIMER1 17
+#define INT_1610_GPTIMER2 18
+#define INT_1610_SSR_FIFO_0 29
+
+#define INT_730_IH2_FIQ 0
+#define INT_730_IH2_IRQ 1
+#define INT_730_USB_NON_ISO 2
+#define INT_730_USB_ISO 3
+#define INT_730_ICR 4
+#define INT_730_EAC 5
+#define INT_730_GPIO_BANK1 6
+#define INT_730_GPIO_BANK2 7
+#define INT_730_GPIO_BANK3 8
+#define INT_730_McBSP2TX 10
+#define INT_730_McBSP2RX 11
+#define INT_730_McBSP2RX_OVF 12
+#define INT_730_LCD_LINE 14
+#define INT_730_GSM_PROTECT 15
+#define INT_730_TIMER3 16
+#define INT_730_GPIO_BANK5 17
+#define INT_730_GPIO_BANK6 18
+#define INT_730_SPGIO_WR 29
+
+#define IH2_BASE 32
+
+#define INT_KEYBOARD (1 + IH2_BASE)
+#define INT_uWireTX (2 + IH2_BASE)
+#define INT_uWireRX (3 + IH2_BASE)
+#define INT_I2C (4 + IH2_BASE)
+#define INT_MPUIO (5 + IH2_BASE)
+#define INT_USB_HHC_1 (6 + IH2_BASE)
+#define INT_McBSP3TX (10 + IH2_BASE)
+#define INT_McBSP3RX (11 + IH2_BASE)
+#define INT_McBSP1TX (12 + IH2_BASE)
+#define INT_McBSP1RX (13 + IH2_BASE)
+#define INT_UART2 (14 + IH2_BASE)
+#define INT_UART1 (15 + IH2_BASE)
+#define INT_BT_MCSI1TX (16 + IH2_BASE)
+#define INT_BT_MCSI1RX (17 + IH2_BASE)
+#define INT_USB_W2FC (20 + IH2_BASE)
+#define INT_1WIRE (21 + IH2_BASE)
+#define INT_OS_TIMER (22 + IH2_BASE)
+#define INT_MMC (23 + IH2_BASE)
+#define INT_GAUGE_32K (24 + IH2_BASE)
+#define INT_RTC_TIMER (25 + IH2_BASE)
+#define INT_RTC_ALARM (26 + IH2_BASE)
+#define INT_MEM_STICK (27 + IH2_BASE)
+#define INT_DSP_MMU (28 + IH2_BASE)
+
+#define INT_1510_COM_SPI_RO (31 + IH2_BASE)
+
+#define INT_1610_FAC (0 + IH2_BASE)
+#define INT_1610_USB_HHC_2 (7 + IH2_BASE)
+#define INT_1610_USB_OTG (8 + IH2_BASE)
+#define INT_1610_SoSSI (9 + IH2_BASE)
+#define INT_1610_SoSSI_MATCH (19 + IH2_BASE)
+#define INT_1610_McBSP2RX_OF (31 + IH2_BASE)
+#define INT_1610_STI (32 + IH2_BASE)
+#define INT_1610_STI_WAKEUP (33 + IH2_BASE)
+#define INT_1610_GPTIMER3 (34 + IH2_BASE)
+#define INT_1610_GPTIMER4 (35 + IH2_BASE)
+#define INT_1610_GPTIMER5 (36 + IH2_BASE)
+#define INT_1610_GPTIMER6 (37 + IH2_BASE)
+#define INT_1610_GPTIMER7 (38 + IH2_BASE)
+#define INT_1610_GPTIMER8 (39 + IH2_BASE)
+#define INT_1610_GPIO_BANK2 (40 + IH2_BASE)
+#define INT_1610_GPIO_BANK3 (41 + IH2_BASE)
+#define INT_1610_MMC2 (42 + IH2_BASE)
+#define INT_1610_CF (43 + IH2_BASE)
+#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE)
+#define INT_1610_GPIO_BANK4 (48 + IH2_BASE)
+#define INT_1610_SPI (49 + IH2_BASE)
+#define INT_1610_DMA_CH6 (53 + IH2_BASE)
+#define INT_1610_DMA_CH7 (54 + IH2_BASE)
+#define INT_1610_DMA_CH8 (55 + IH2_BASE)
+#define INT_1610_DMA_CH9 (56 + IH2_BASE)
+#define INT_1610_DMA_CH10 (57 + IH2_BASE)
+#define INT_1610_DMA_CH11 (58 + IH2_BASE)
+#define INT_1610_DMA_CH12 (59 + IH2_BASE)
+#define INT_1610_DMA_CH13 (60 + IH2_BASE)
+#define INT_1610_DMA_CH14 (61 + IH2_BASE)
+#define INT_1610_DMA_CH15 (62 + IH2_BASE)
+#define INT_1610_NAND (63 + IH2_BASE)
+
+#define INT_730_HW_ERRORS (0 + IH2_BASE)
+#define INT_730_NFIQ_PWR_FAIL (1 + IH2_BASE)
+#define INT_730_CFCD (2 + IH2_BASE)
+#define INT_730_CFIREQ (3 + IH2_BASE)
+#define INT_730_I2C (4 + IH2_BASE)
+#define INT_730_PCC (5 + IH2_BASE)
+#define INT_730_MPU_EXT_NIRQ (6 + IH2_BASE)
+#define INT_730_SPI_100K_1 (7 + IH2_BASE)
+#define INT_730_SYREN_SPI (8 + IH2_BASE)
+#define INT_730_VLYNQ (9 + IH2_BASE)
+#define INT_730_GPIO_BANK4 (10 + IH2_BASE)
+#define INT_730_McBSP1TX (11 + IH2_BASE)
+#define INT_730_McBSP1RX (12 + IH2_BASE)
+#define INT_730_McBSP1RX_OF (13 + IH2_BASE)
+#define INT_730_UART_MODEM_IRDA_2 (14 + IH2_BASE)
+#define INT_730_UART_MODEM_1 (15 + IH2_BASE)
+#define INT_730_MCSI (16 + IH2_BASE)
+#define INT_730_uWireTX (17 + IH2_BASE)
+#define INT_730_uWireRX (18 + IH2_BASE)
+#define INT_730_SMC_CD (19 + IH2_BASE)
+#define INT_730_SMC_IREQ (20 + IH2_BASE)
+#define INT_730_HDQ_1WIRE (21 + IH2_BASE)
+#define INT_730_TIMER32K (22 + IH2_BASE)
+#define INT_730_MMC_SDIO (23 + IH2_BASE)
+#define INT_730_UPLD (24 + IH2_BASE)
+#define INT_730_USB_HHC_1 (27 + IH2_BASE)
+#define INT_730_USB_HHC_2 (28 + IH2_BASE)
+#define INT_730_USB_GENI (29 + IH2_BASE)
+#define INT_730_USB_OTG (30 + IH2_BASE)
+#define INT_730_CAMERA_IF (31 + IH2_BASE)
+#define INT_730_RNG (32 + IH2_BASE)
+#define INT_730_DUAL_MODE_TIMER (33 + IH2_BASE)
+#define INT_730_DBB_RF_EN (34 + IH2_BASE)
+#define INT_730_MPUIO_KEYPAD (35 + IH2_BASE)
+#define INT_730_SHA1_MD5 (36 + IH2_BASE)
+#define INT_730_SPI_100K_2 (37 + IH2_BASE)
+#define INT_730_RNG_IDLE (38 + IH2_BASE)
+#define INT_730_MPUIO (39 + IH2_BASE)
+#define INT_730_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
+#define INT_730_LLPC_OE_FALLING (41 + IH2_BASE)
+#define INT_730_LLPC_OE_RISING (42 + IH2_BASE)
+#define INT_730_LLPC_VSYNC (43 + IH2_BASE)
+#define INT_730_WAKE_UP_REQ (46 + IH2_BASE)
+#define INT_730_DMA_CH6 (53 + IH2_BASE)
+#define INT_730_DMA_CH7 (54 + IH2_BASE)
+#define INT_730_DMA_CH8 (55 + IH2_BASE)
+#define INT_730_DMA_CH9 (56 + IH2_BASE)
+#define INT_730_DMA_CH10 (57 + IH2_BASE)
+#define INT_730_DMA_CH11 (58 + IH2_BASE)
+#define INT_730_DMA_CH12 (59 + IH2_BASE)
+#define INT_730_DMA_CH13 (60 + IH2_BASE)
+#define INT_730_DMA_CH14 (61 + IH2_BASE)
+#define INT_730_DMA_CH15 (62 + IH2_BASE)
+#define INT_730_NAND (63 + IH2_BASE)
+
+#define INT_24XX_SYS_NIRQ 7
+#define INT_24XX_SDMA_IRQ0 12
+#define INT_24XX_SDMA_IRQ1 13
+#define INT_24XX_SDMA_IRQ2 14
+#define INT_24XX_SDMA_IRQ3 15
+#define INT_24XX_CAM_IRQ 24
+#define INT_24XX_DSS_IRQ 25
+#define INT_24XX_GPIO_BANK1 29
+#define INT_24XX_GPIO_BANK2 30
+#define INT_24XX_GPIO_BANK3 31
+#define INT_24XX_GPIO_BANK4 32
+#define INT_24XX_GPTIMER1 37
+#define INT_24XX_GPTIMER2 38
+#define INT_24XX_GPTIMER3 39
+#define INT_24XX_GPTIMER4 40
+#define INT_24XX_GPTIMER5 41
+#define INT_24XX_GPTIMER6 42
+#define INT_24XX_GPTIMER7 43
+#define INT_24XX_GPTIMER8 44
+#define INT_24XX_GPTIMER9 45
+#define INT_24XX_GPTIMER10 46
+#define INT_24XX_GPTIMER11 47
+#define INT_24XX_GPTIMER12 48
+#define INT_24XX_MCBSP1_IRQ_TX 59
+#define INT_24XX_MCBSP1_IRQ_RX 60
+#define INT_24XX_MCBSP2_IRQ_TX 62
+#define INT_24XX_MCBSP2_IRQ_RX 63
+#define INT_24XX_UART1_IRQ 72
+#define INT_24XX_UART2_IRQ 73
+#define INT_24XX_UART3_IRQ 74
+#define INT_24XX_MMC_IRQ 83
+
+#define OMAP_MAX_GPIO_LINES 192
+#define IH_GPIO_BASE (128 + IH2_BASE)
+#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
+#define IH_BOARD_BASE (16 + IH_MPUIO_BASE)
+
+#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
+
+#ifndef __ASSEMBLY__
+
+#endif
+
+#include <asm/hardware.h>
+
+#ifndef NR_IRQS
+#define NR_IRQS IH_BOARD_BASE
+#endif
+
+#endif
diff --git a/libc/kernel/arch-arm/asm/arch/mcbsp.h b/libc/kernel/arch-arm/asm/arch/mcbsp.h
new file mode 100644
index 0000000..cae5e3b
--- /dev/null
+++ b/libc/kernel/arch-arm/asm/arch/mcbsp.h
@@ -0,0 +1,185 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef __ASM_ARCH_OMAP_MCBSP_H
+#define __ASM_ARCH_OMAP_MCBSP_H
+
+#include <asm/hardware.h>
+
+#define OMAP730_MCBSP1_BASE 0xfffb1000
+#define OMAP730_MCBSP2_BASE 0xfffb1800
+
+#define OMAP1510_MCBSP1_BASE 0xe1011800
+#define OMAP1510_MCBSP2_BASE 0xfffb1000
+#define OMAP1510_MCBSP3_BASE 0xe1017000
+
+#define OMAP1610_MCBSP1_BASE 0xe1011800
+#define OMAP1610_MCBSP2_BASE 0xfffb1000
+#define OMAP1610_MCBSP3_BASE 0xe1017000
+
+#define OMAP24XX_MCBSP1_BASE 0x48074000
+#define OMAP24XX_MCBSP2_BASE 0x48076000
+
+#define OMAP_MCBSP_READ(base, reg) __raw_readw((base) + OMAP_MCBSP_REG_##reg)
+#define OMAP_MCBSP_WRITE(base, reg, val) __raw_writew((val), (base) + OMAP_MCBSP_REG_##reg)
+
+#define RRST 0x0001
+#define RRDY 0x0002
+#define RFULL 0x0004
+#define RSYNC_ERR 0x0008
+#define RINTM(value) ((value)<<4)  
+#define ABIS 0x0040
+#define DXENA 0x0080
+#define CLKSTP(value) ((value)<<11)  
+#define RJUST(value) ((value)<<13)  
+#define DLB 0x8000
+
+#define XRST 0x0001
+#define XRDY 0x0002
+#define XEMPTY 0x0004
+#define XSYNC_ERR 0x0008
+#define XINTM(value) ((value)<<4)  
+#define GRST 0x0040
+#define FRST 0x0080
+#define SOFT 0x0100
+#define FREE 0x0200
+
+#define CLKRP 0x0001
+#define CLKXP 0x0002
+#define FSRP 0x0004
+#define FSXP 0x0008
+#define DR_STAT 0x0010
+#define DX_STAT 0x0020
+#define CLKS_STAT 0x0040
+#define SCLKME 0x0080
+#define CLKRM 0x0100
+#define CLKXM 0x0200
+#define FSRM 0x0400
+#define FSXM 0x0800
+#define RIOEN 0x1000
+#define XIOEN 0x2000
+#define IDLE_EN 0x4000
+
+#define RWDLEN1(value) ((value)<<5)  
+#define RFRLEN1(value) ((value)<<8)  
+
+#define XWDLEN1(value) ((value)<<5)  
+#define XFRLEN1(value) ((value)<<8)  
+
+#define RDATDLY(value) (value)  
+#define RFIG 0x0004
+#define RCOMPAND(value) ((value)<<3)  
+#define RWDLEN2(value) ((value)<<5)  
+#define RFRLEN2(value) ((value)<<8)  
+#define RPHASE 0x8000
+
+#define XDATDLY(value) (value)  
+#define XFIG 0x0004
+#define XCOMPAND(value) ((value)<<3)  
+#define XWDLEN2(value) ((value)<<5)  
+#define XFRLEN2(value) ((value)<<8)  
+#define XPHASE 0x8000
+
+#define CLKGDV(value) (value)  
+#define FWID(value) ((value)<<8)  
+
+#define FPER(value) (value)  
+#define FSGM 0x1000
+#define CLKSM 0x2000
+#define CLKSP 0x4000
+#define GSYNC 0x8000
+
+#define RMCM 0x0001
+#define RCBLK(value) ((value)<<2)  
+#define RPABLK(value) ((value)<<5)  
+#define RPBBLK(value) ((value)<<7)  
+
+#define XMCM(value) (value)  
+#define XCBLK(value) ((value)<<2)  
+#define XPABLK(value) ((value)<<5)  
+#define XPBBLK(value) ((value)<<7)  
+
+struct omap_mcbsp_reg_cfg {
+ u16 spcr2;
+ u16 spcr1;
+ u16 rcr2;
+ u16 rcr1;
+ u16 xcr2;
+ u16 xcr1;
+ u16 srgr2;
+ u16 srgr1;
+ u16 mcr2;
+ u16 mcr1;
+ u16 pcr0;
+ u16 rcerc;
+ u16 rcerd;
+ u16 xcerc;
+ u16 xcerd;
+ u16 rcere;
+ u16 rcerf;
+ u16 xcere;
+ u16 xcerf;
+ u16 rcerg;
+ u16 rcerh;
+ u16 xcerg;
+ u16 xcerh;
+};
+
+typedef enum {
+ OMAP_MCBSP1 = 0,
+ OMAP_MCBSP2,
+ OMAP_MCBSP3,
+} omap_mcbsp_id;
+
+typedef int __bitwise omap_mcbsp_io_type_t;
+#define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
+#define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
+
+typedef enum {
+ OMAP_MCBSP_WORD_8 = 0,
+ OMAP_MCBSP_WORD_12,
+ OMAP_MCBSP_WORD_16,
+ OMAP_MCBSP_WORD_20,
+ OMAP_MCBSP_WORD_24,
+ OMAP_MCBSP_WORD_32,
+} omap_mcbsp_word_length;
+
+typedef enum {
+ OMAP_MCBSP_CLK_RISING = 0,
+ OMAP_MCBSP_CLK_FALLING,
+} omap_mcbsp_clk_polarity;
+
+typedef enum {
+ OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
+ OMAP_MCBSP_FS_ACTIVE_LOW,
+} omap_mcbsp_fs_polarity;
+
+typedef enum {
+ OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
+ OMAP_MCBSP_CLK_STP_MODE_DELAY,
+} omap_mcbsp_clk_stp_mode;
+
+typedef enum {
+ OMAP_MCBSP_SPI_MASTER = 0,
+ OMAP_MCBSP_SPI_SLAVE,
+} omap_mcbsp_spi_mode;
+
+struct omap_mcbsp_spi_cfg {
+ omap_mcbsp_spi_mode spi_mode;
+ omap_mcbsp_clk_polarity rx_clock_polarity;
+ omap_mcbsp_clk_polarity tx_clock_polarity;
+ omap_mcbsp_fs_polarity fsx_polarity;
+ u8 clk_div;
+ omap_mcbsp_clk_stp_mode clk_stp_mode;
+ omap_mcbsp_word_length word_length;
+};
+
+#endif
diff --git a/libc/kernel/arch-arm/asm/arch/memory.h b/libc/kernel/arch-arm/asm/arch/memory.h
new file mode 100644
index 0000000..8b064b8
--- /dev/null
+++ b/libc/kernel/arch-arm/asm/arch/memory.h
@@ -0,0 +1,19 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt(x) __phys_to_virt(x)
+
+#endif
+
diff --git a/libc/kernel/arch-arm/asm/arch/mtd-xip.h b/libc/kernel/arch-arm/asm/arch/mtd-xip.h
new file mode 100644
index 0000000..9b60aef
--- /dev/null
+++ b/libc/kernel/arch-arm/asm/arch/mtd-xip.h
@@ -0,0 +1,31 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef __ARCH_OMAP_MTD_XIP_H__
+#define __ARCH_OMAP_MTD_XIP_H__
+
+#include <asm/hardware.h>
+#define OMAP_MPU_TIMER_BASE (0xfffec500)
+#define OMAP_MPU_TIMER_OFFSET 0x100
+
+typedef struct {
+ u32 cntl;
+ u32 load_tim;
+ u32 read_tim;
+} xip_omap_mpu_timer_regs_t;
+
+#define xip_omap_mpu_timer_base(n)  ((volatile xip_omap_mpu_timer_regs_t*)IO_ADDRESS(OMAP_MPU_TIMER_BASE +   (n)*OMAP_MPU_TIMER_OFFSET))
+
+#define xip_irqpending()   (omap_readl(OMAP_IH1_ITR) & ~omap_readl(OMAP_IH1_MIR))
+#define xip_currtime() (~xip_omap_mpu_timer_read(0))
+#define xip_elapsed_since(x) (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 6)
+#define xip_cpu_idle() asm volatile ("mcr p15, 0, %0, c7, c0, 4" :: "r" (1))
+#endif
diff --git a/libc/kernel/arch-arm/asm/arch/mux.h b/libc/kernel/arch-arm/asm/arch/mux.h
new file mode 100644
index 0000000..72da54e
--- /dev/null
+++ b/libc/kernel/arch-arm/asm/arch/mux.h
@@ -0,0 +1,391 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef __ASM_ARCH_MUX_H
+#define __ASM_ARCH_MUX_H
+
+#define PU_PD_SEL_NA 0  
+#define PULL_DWN_CTRL_NA 0  
+
+#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg,   .mask_offset = mode_offset,   .mask = mode,
+
+#define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg,   .pull_bit = bit,   .pull_val = status,
+
+#define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg,   .pu_pd_val = status,
+
+#define MUX_REG_730(reg, mode_offset, mode)   .mux_reg = OMAP730_IO_CONF_##reg,   .mask_offset = mode_offset,   .mask = mode,
+
+#define PULL_REG_730(reg, bit, status) .pull_reg = OMAP730_IO_CONF_##reg,   .pull_bit = bit,   .pull_val = status,
+
+#define MUX_CFG(desc, mux_reg, mode_offset, mode,   pull_reg, pull_bit, pull_status,   pu_pd_reg, pu_pd_status, debug_status)  {   .name = desc,   .debug = debug_status,   MUX_REG(mux_reg, mode_offset, mode)   PULL_REG(pull_reg, pull_bit, !pull_status)   PU_PD_REG(pu_pd_reg, pu_pd_status)  },
+
+#define MUX_CFG_730(desc, mux_reg, mode_offset, mode,   pull_bit, pull_status, debug_status) {   .name = desc,   .debug = debug_status,   MUX_REG_730(mux_reg, mode_offset, mode)   PULL_REG_730(mux_reg, pull_bit, pull_status)   PU_PD_REG(NA, 0)  },
+
+#define MUX_CFG_24XX(desc, reg_offset, mode,   pull_en, pull_mode, dbg)  {   .name = desc,   .debug = dbg,   .mux_reg = reg_offset,   .mask = mode,   .pull_val = pull_en,   .pu_pd_val = pull_mode,  },
+
+#define PULL_DISABLED 0
+#define PULL_ENABLED 1
+
+#define PULL_DOWN 0
+#define PULL_UP 1
+
+struct pin_config {
+ char *name;
+ unsigned char busy;
+ unsigned char debug;
+
+ const char *mux_reg_name;
+ const unsigned int mux_reg;
+ const unsigned char mask_offset;
+ const unsigned char mask;
+
+ const char *pull_name;
+ const unsigned int pull_reg;
+ const unsigned char pull_val;
+ const unsigned char pull_bit;
+
+ const char *pu_pd_name;
+ const unsigned int pu_pd_reg;
+ const unsigned char pu_pd_val;
+};
+
+enum omap730_index {
+
+ E2_730_KBR0,
+ J7_730_KBR1,
+ E1_730_KBR2,
+ F3_730_KBR3,
+ D2_730_KBR4,
+ AA20_730_KBR5,
+ V17_730_KBR6,
+ C2_730_KBC0,
+ D3_730_KBC1,
+ E4_730_KBC2,
+ F4_730_KBC3,
+ E3_730_KBC4,
+
+ AA17_730_USB_DM,
+ W16_730_USB_PU_EN,
+ W17_730_USB_VBUSI,
+
+ V19_730_GPIO_15,
+ M19_730_GPIO_77,
+ C21_730_GPIO_121_122,
+ K19_730_GPIO_126,
+ K15_730_GPIO_127,
+
+ P15_730_GPIO_16_17,
+
+ M15_730_GPIO_83,
+ N20_730_GPIO_82,
+ N18_730_GPIO_81,
+ N19_730_GPIO_80,
+ L15_730_GPIO_76,
+
+ UART1_CTS_RTS,
+ OMAP_730_GPIOS_42_43,
+ UART1_TX_RX,
+ OMAP_730_GPIOS_40_41,
+ UART1_USB_RX_TX,
+ UART1_USB_RTS,
+ UART1_USB_CTS
+};
+
+enum omap1xxx_index {
+
+ UART1_TX = 0,
+ UART1_RTS,
+
+ UART2_TX,
+ UART2_RX,
+ UART2_CTS,
+ UART2_RTS,
+
+ UART3_TX,
+ UART3_RX,
+ UART3_CTS,
+ UART3_RTS,
+ UART3_CLKREQ,
+ UART3_BCLK,
+ Y15_1610_UART3_RTS,
+
+ PWT,
+ PWL,
+
+ R18_USB_VBUS,
+ R18_1510_USB_GPIO0,
+ W4_USB_PUEN,
+ W4_USB_CLKO,
+ W4_USB_HIGHZ,
+ W4_GPIO58,
+
+ USB1_SUSP,
+ USB1_SEO,
+ W13_1610_USB1_SE0,
+ USB1_TXEN,
+ USB1_TXD,
+ USB1_VP,
+ USB1_VM,
+ USB1_RCV,
+ USB1_SPEED,
+ R13_1610_USB1_SPEED,
+ R13_1710_USB1_SE0,
+
+ USB2_SUSP,
+ USB2_VP,
+ USB2_TXEN,
+ USB2_VM,
+ USB2_RCV,
+ USB2_SEO,
+ USB2_TXD,
+
+ R18_1510_GPIO0,
+ R19_1510_GPIO1,
+ M14_1510_GPIO2,
+
+ P18_1610_GPIO3,
+ Y15_1610_GPIO17,
+
+ R18_1710_GPIO0,
+ V2_1710_GPIO10,
+ N21_1710_GPIO14,
+ W15_1710_GPIO40,
+
+ MPUIO2,
+ N15_1610_MPUIO2,
+ MPUIO4,
+ MPUIO5,
+ T20_1610_MPUIO5,
+ W11_1610_MPUIO6,
+ V10_1610_MPUIO7,
+ W11_1610_MPUIO9,
+ V10_1610_MPUIO10,
+ W10_1610_MPUIO11,
+ E20_1610_MPUIO13,
+ U20_1610_MPUIO14,
+ E19_1610_MPUIO15,
+
+ MCBSP2_CLKR,
+ MCBSP2_CLKX,
+ MCBSP2_DR,
+ MCBSP2_DX,
+ MCBSP2_FSR,
+ MCBSP2_FSX,
+
+ MCBSP3_CLKX,
+
+ BALLOUT_V8_ARMIO3,
+ N20_HDQ,
+
+ W8_1610_MMC2_DAT0,
+ V8_1610_MMC2_DAT1,
+ W15_1610_MMC2_DAT2,
+ R10_1610_MMC2_DAT3,
+ Y10_1610_MMC2_CLK,
+ Y8_1610_MMC2_CMD,
+ V9_1610_MMC2_CMDDIR,
+ V5_1610_MMC2_DATDIR0,
+ W19_1610_MMC2_DATDIR1,
+ R18_1610_MMC2_CLKIN,
+
+ M19_1610_ETM_PSTAT0,
+ L15_1610_ETM_PSTAT1,
+ L18_1610_ETM_PSTAT2,
+ L19_1610_ETM_D0,
+ J19_1610_ETM_D6,
+ J18_1610_ETM_D7,
+
+ P20_1610_GPIO4,
+ V9_1610_GPIO7,
+ W8_1610_GPIO9,
+ N20_1610_GPIO11,
+ N19_1610_GPIO13,
+ P10_1610_GPIO22,
+ V5_1610_GPIO24,
+ AA20_1610_GPIO_41,
+ W19_1610_GPIO48,
+ M7_1610_GPIO62,
+ V14_16XX_GPIO37,
+ R9_16XX_GPIO18,
+ L14_16XX_GPIO49,
+
+ V19_1610_UWIRE_SCLK,
+ U18_1610_UWIRE_SDI,
+ W21_1610_UWIRE_SDO,
+ N14_1610_UWIRE_CS0,
+ P15_1610_UWIRE_CS3,
+ N15_1610_UWIRE_CS1,
+
+ U19_1610_SPIF_SCK,
+ U18_1610_SPIF_DIN,
+ P20_1610_SPIF_DIN,
+ W21_1610_SPIF_DOUT,
+ R18_1610_SPIF_DOUT,
+ N14_1610_SPIF_CS0,
+ N15_1610_SPIF_CS1,
+ T19_1610_SPIF_CS2,
+ P15_1610_SPIF_CS3,
+
+ L3_1610_FLASH_CS2B_OE,
+ M8_1610_FLASH_CS2B_WE,
+
+ MMC_CMD,
+ MMC_DAT1,
+ MMC_DAT2,
+ MMC_DAT0,
+ MMC_CLK,
+ MMC_DAT3,
+
+ M15_1710_MMC_CLKI,
+ P19_1710_MMC_CMDDIR,
+ P20_1710_MMC_DATDIR0,
+
+ W9_USB0_TXEN,
+ AA9_USB0_VP,
+ Y5_USB0_RCV,
+ R9_USB0_VM,
+ V6_USB0_TXD,
+ W5_USB0_SE0,
+ V9_USB0_SPEED,
+ V9_USB0_SUSP,
+
+ W9_USB2_TXEN,
+ AA9_USB2_VP,
+ Y5_USB2_RCV,
+ R9_USB2_VM,
+ V6_USB2_TXD,
+ W5_USB2_SE0,
+
+ R13_1610_UART1_TX,
+ V14_16XX_UART1_RX,
+ R14_1610_UART1_CTS,
+ AA15_1610_UART1_RTS,
+ R9_16XX_UART2_RX,
+ L14_16XX_UART3_RX,
+
+ I2C_SCL,
+ I2C_SDA,
+
+ F18_1610_KBC0,
+ D20_1610_KBC1,
+ D19_1610_KBC2,
+ E18_1610_KBC3,
+ C21_1610_KBC4,
+ G18_1610_KBR0,
+ F19_1610_KBR1,
+ H14_1610_KBR2,
+ E20_1610_KBR3,
+ E19_1610_KBR4,
+ N19_1610_KBR5,
+
+ T20_1610_LOW_PWR,
+
+ V5_1710_MCLK_ON,
+ V5_1710_MCLK_OFF,
+ R10_1610_MCLK_ON,
+ R10_1610_MCLK_OFF,
+
+ P11_1610_CF_CD2,
+ R11_1610_CF_IOIS16,
+ V10_1610_CF_IREQ,
+ W10_1610_CF_RESET,
+ W11_1610_CF_CD1,
+};
+
+enum omap24xx_index {
+
+ M19_24XX_I2C1_SCL,
+ L15_24XX_I2C1_SDA,
+ J15_24XX_I2C2_SCL,
+ H19_24XX_I2C2_SDA,
+
+ W19_24XX_SYS_NIRQ,
+
+ W14_24XX_SYS_CLKOUT,
+
+ L3_GPMC_WAIT0,
+ N7_GPMC_WAIT1,
+ M1_GPMC_WAIT2,
+ P1_GPMC_WAIT3,
+
+ Y15_24XX_MCBSP2_CLKX,
+ R14_24XX_MCBSP2_FSX,
+ W15_24XX_MCBSP2_DR,
+ V15_24XX_MCBSP2_DX,
+
+ M21_242X_GPIO11,
+ AA10_242X_GPIO13,
+ AA6_242X_GPIO14,
+ AA4_242X_GPIO15,
+ Y11_242X_GPIO16,
+ AA12_242X_GPIO17,
+ AA8_242X_GPIO58,
+ Y20_24XX_GPIO60,
+ W4__24XX_GPIO74,
+ M15_24XX_GPIO92,
+ V14_24XX_GPIO117,
+
+ V4_242X_GPIO49,
+ W2_242X_GPIO50,
+ U4_242X_GPIO51,
+ V3_242X_GPIO52,
+ V2_242X_GPIO53,
+ V6_242X_GPIO53,
+ T4_242X_GPIO54,
+ Y4_242X_GPIO54,
+ T3_242X_GPIO55,
+ U2_242X_GPIO56,
+
+ AA10_242X_DMAREQ0,
+ AA6_242X_DMAREQ1,
+ E4_242X_DMAREQ2,
+ G4_242X_DMAREQ3,
+ D3_242X_DMAREQ4,
+ E3_242X_DMAREQ5,
+
+ P20_24XX_TSC_IRQ,
+
+ K15_24XX_UART3_TX,
+ K14_24XX_UART3_RX,
+
+ G19_24XX_MMC_CLKO,
+ H18_24XX_MMC_CMD,
+ F20_24XX_MMC_DAT0,
+ H14_24XX_MMC_DAT1,
+ E19_24XX_MMC_DAT2,
+ D19_24XX_MMC_DAT3,
+ F19_24XX_MMC_DAT_DIR0,
+ E20_24XX_MMC_DAT_DIR1,
+ F18_24XX_MMC_DAT_DIR2,
+ E18_24XX_MMC_DAT_DIR3,
+ G18_24XX_MMC_CMD_DIR,
+ H15_24XX_MMC_CLKI,
+
+ T19_24XX_KBR0,
+ R19_24XX_KBR1,
+ V18_24XX_KBR2,
+ M21_24XX_KBR3,
+ E5__24XX_KBR4,
+ M18_24XX_KBR5,
+ R20_24XX_KBC0,
+ M14_24XX_KBC1,
+ H19_24XX_KBC2,
+ V17_24XX_KBC3,
+ P21_24XX_KBC4,
+ L14_24XX_KBC5,
+ N19_24XX_KBC6,
+
+ B3__24XX_KBR5,
+ AA4_24XX_KBC2,
+ B13_24XX_KBC6,
+};
+
+#endif
diff --git a/libc/kernel/arch-arm/asm/arch/omap24xx.h b/libc/kernel/arch-arm/asm/arch/omap24xx.h
new file mode 100644
index 0000000..37def2f
--- /dev/null
+++ b/libc/kernel/arch-arm/asm/arch/omap24xx.h
@@ -0,0 +1,30 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef __ASM_ARCH_OMAP24XX_H
+#define __ASM_ARCH_OMAP24XX_H
+
+#define L4_24XX_BASE 0x48000000
+#define L3_24XX_BASE 0x68000000
+
+#define OMAP24XX_IC_BASE (L4_24XX_BASE + 0xfe000)
+#define VA_IC_BASE IO_ADDRESS(OMAP24XX_IC_BASE)
+#define OMAP24XX_IVA_INTC_BASE 0x40000000
+#define IRQ_SIR_IRQ 0x0040
+
+#define OMAP24XX_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
+#define OMAP24XX_PRCM_BASE (L4_24XX_BASE + 0x8000)
+#define OMAP24XX_SDRC_BASE (L3_24XX_BASE + 0x9000)
+
+#define OMAP242X_CONTROL_STATUS (L4_24XX_BASE + 0x2f8)
+
+#endif
+
diff --git a/libc/kernel/arch-arm/asm/arch/serial.h b/libc/kernel/arch-arm/asm/arch/serial.h
new file mode 100644
index 0000000..6ab8613
--- /dev/null
+++ b/libc/kernel/arch-arm/asm/arch/serial.h
@@ -0,0 +1,21 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef __ASM_ARCH_SERIAL_H
+#define __ASM_ARCH_SERIAL_H
+
+#define OMAP_MAX_NR_PORTS 3
+#define OMAP1510_BASE_BAUD (12000000/16)
+#define OMAP16XX_BASE_BAUD (48000000/16)
+
+#define is_omap_port(p) ({int __ret = 0;   if (p == IO_ADDRESS(OMAP_UART1_BASE) ||   p == IO_ADDRESS(OMAP_UART2_BASE) ||   p == IO_ADDRESS(OMAP_UART3_BASE))   __ret = 1;   __ret;   })
+
+#endif
diff --git a/libc/kernel/arch-arm/asm/arch/timex.h b/libc/kernel/arch-arm/asm/arch/timex.h
new file mode 100644
index 0000000..2c9234c
--- /dev/null
+++ b/libc/kernel/arch-arm/asm/arch/timex.h
@@ -0,0 +1,17 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef __ASM_ARCH_OMAP_TIMEX_H
+#define __ASM_ARCH_OMAP_TIMEX_H
+
+#define CLOCK_TICK_RATE (HZ * 100000UL)
+
+#endif
diff --git a/libc/kernel/arch-arm/asm/arch/vmalloc.h b/libc/kernel/arch-arm/asm/arch/vmalloc.h
new file mode 100644
index 0000000..f2b5b44
--- /dev/null
+++ b/libc/kernel/arch-arm/asm/arch/vmalloc.h
@@ -0,0 +1,13 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
+