Add a unittest for the CPU class.

This change just adds a unit test "CPU.RunExtendedInstructions" to base_unittests, which runs extended instructions for each CPU member function.

BUG=none
TEST=CPU.RunExtendedInstructions
Review URL: http://codereview.chromium.org/6548003

git-svn-id: svn://svn.chromium.org/chrome/trunk/src@75861 0039d316-1c4b-4281-b951-d872f2087c98

2 files changed, 94 insertions, 2 deletions

diff --git a/base/base.gyp b/base/base.gyp
index 868569e..525d316 100644
--- a/base/base.gyp
+++ b/base/base.gyp
@@ -31,8 +31,8 @@
         'base',
       ],
       'sources': [
-	'i18n/bidi_line_iterator.cc',
-	'i18n/bidi_line_iterator.h',
+        'i18n/bidi_line_iterator.cc',
+        'i18n/bidi_line_iterator.h',
         'i18n/break_iterator.cc',
         'i18n/break_iterator.h',
         'i18n/char_iterator.cc',
@@ -69,6 +69,7 @@
         'bits_unittest.cc',
         'callback_unittest.cc',
         'command_line_unittest.cc',
+        'cpu_unittest.cc',
         'crypto/encryptor_unittest.cc',
         'crypto/rsa_private_key_unittest.cc',
         'crypto/rsa_private_key_nss_unittest.cc',
diff --git a/base/cpu_unittest.cc b/base/cpu_unittest.cc
new file mode 100644
index 0000000..a27502e
--- /dev/null
+++ b/base/cpu_unittest.cc
@@ -0,0 +1,91 @@
+// Copyright (c) 2011 The Chromium Authors. All rights reserved.
+// Use of this source code is governed by a BSD-style license that can be
+// found in the LICENSE file.
+
+#include "base/cpu.h"
+
+#include "testing/gtest/include/gtest/gtest.h"
+
+// Tests whether we can run extended instructions represented by the CPU
+// information. This test actually executes some extended instructions (such as
+// MMX, SSE, etc.) supported by the CPU and sees we can run them without
+// "undefined instruction" exceptions. That is, this test succeeds when this
+// test finishes without a crash.
+TEST(CPU, RunExtendedInstructions) {
+#if defined(ARCH_CPU_X86_FAMILY)
+  // Retrieve the CPU information.
+  base::CPU cpu;
+
+#if defined(OS_WIN)
+  ASSERT_TRUE(cpu.has_mmx());
+
+  // Execute an MMX instruction.
+  __asm emms;
+
+  if (cpu.has_sse()) {
+    // Execute an SSE instruction.
+    __asm xorps xmm0, xmm0;
+  }
+
+  if (cpu.has_sse2()) {
+    // Execute an SSE 2 instruction.
+    __asm psrldq xmm0, 0;
+  }
+
+  if (cpu.has_sse3()) {
+    // Execute an SSE 3 instruction.
+    __asm addsubpd xmm0, xmm0;
+  }
+
+  if (cpu.has_ssse3()) {
+    // Execute a Supplimental SSE 3 instruction.
+    __asm psignb xmm0, xmm0;
+  }
+
+  if (cpu.has_sse41()) {
+    // Execute an SSE 4.1 instruction.
+    __asm pmuldq xmm0, xmm0;
+  }
+
+  if (cpu.has_sse42()) {
+    // Execute an SSE 4.2 instruction.
+    __asm crc32 eax, eax;
+  }
+#elif defined(OS_POSIX)
+  ASSERT_TRUE(cpu.has_mmx());
+
+  // Execute an MMX instruction.
+  __asm__ __volatile__("emms\n" : : : "mm0");
+
+  if (cpu.has_sse()) {
+    // Execute an SSE instruction.
+    __asm__ __volatile__("xorps %%xmm0, %%xmm0\n" : : : "xmm0");
+  }
+
+  if (cpu.has_sse2()) {
+    // Execute an SSE 2 instruction.
+    __asm__ __volatile__("psrldq $0, %%xmm0\n" : : : "xmm0");
+  }
+
+  if (cpu.has_sse3()) {
+    // Execute an SSE 3 instruction.
+    __asm__ __volatile__("addsubpd %%xmm0, %%xmm0\n" : : : "xmm0");
+  }
+
+  if (cpu.has_ssse3()) {
+    // Execute a Supplimental SSE 3 instruction.
+    __asm__ __volatile__("psignb %%xmm0, %%xmm0\n" : : : "xmm0");
+  }
+
+  if (cpu.has_sse41()) {
+    // Execute an SSE 4.1 instruction.
+    __asm__ __volatile__("pmuldq %%xmm0, %%xmm0\n" : : : "xmm0");
+  }
+
+  if (cpu.has_sse42()) {
+    // Execute an SSE 4.2 instruction.
+    __asm__ __volatile__("crc32 %%eax, %%eax\n" : : : "eax");
+  }
+#endif
+#endif
+}