gralloc: use headers from drm and mesa instead of local copy

Patch removes local outdated headers for intel hw and starts
to depend on ones from libdrm and mesa projects, this makes sure
we are up to date with new pci id's etc.

intel_init_kms_features required some fixing because of changed
macros, patch also adds GEN7 check in place for IVB and HSW.

Change-Id: Iee6375ceb558baf4334e3b9b5d26210406aa7b71
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>

4 files changed, 6 insertions, 217 deletions

diff --git a/dri/intel_chipset.h b/dri/intel_chipset.h
deleted file mode 100644
index 2e9fb2d..0000000
--- a/dri/intel_chipset.h
+++ /dev/null
@@ -1,172 +0,0 @@
- /*
- * Copyright © 2007 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- *    Eric Anholt <eric@anholt.net>
- *
- */
-
-#define PCI_CHIP_I810			0x7121
-#define PCI_CHIP_I810_DC100		0x7123
-#define PCI_CHIP_I810_E			0x7125
-#define PCI_CHIP_I815			0x1132
-
-#define PCI_CHIP_I830_M			0x3577
-#define PCI_CHIP_845_G			0x2562
-#define PCI_CHIP_I855_GM		0x3582
-#define PCI_CHIP_I865_G			0x2572
-
-#define PCI_CHIP_I915_G			0x2582
-#define PCI_CHIP_E7221_G		0x258A
-#define PCI_CHIP_I915_GM		0x2592
-#define PCI_CHIP_I945_G			0x2772
-#define PCI_CHIP_I945_GM		0x27A2
-#define PCI_CHIP_I945_GME		0x27AE
-
-#define PCI_CHIP_Q35_G			0x29B2
-#define PCI_CHIP_G33_G			0x29C2
-#define PCI_CHIP_Q33_G			0x29D2
-
-#define PCI_CHIP_IGD_GM			0xA011
-#define PCI_CHIP_IGD_G			0xA001
-
-#define IS_IGDGM(devid)	(devid == PCI_CHIP_IGD_GM)
-#define IS_IGDG(devid)	(devid == PCI_CHIP_IGD_G)
-#define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid))
-
-#define PCI_CHIP_I965_G			0x29A2
-#define PCI_CHIP_I965_Q			0x2992
-#define PCI_CHIP_I965_G_1		0x2982
-#define PCI_CHIP_I946_GZ		0x2972
-#define PCI_CHIP_I965_GM                0x2A02
-#define PCI_CHIP_I965_GME               0x2A12
-
-#define PCI_CHIP_GM45_GM                0x2A42
-
-#define PCI_CHIP_IGD_E_G                0x2E02
-#define PCI_CHIP_Q45_G                  0x2E12
-#define PCI_CHIP_G45_G                  0x2E22
-#define PCI_CHIP_G41_G                  0x2E32
-#define PCI_CHIP_B43_G                  0x2E42
-#define PCI_CHIP_B43_G1                 0x2E92
-
-#define PCI_CHIP_ILD_G                  0x0042
-#define PCI_CHIP_ILM_G                  0x0046
-
-#define PCI_CHIP_SANDYBRIDGE_GT1	0x0102	/* Desktop */
-#define PCI_CHIP_SANDYBRIDGE_GT2	0x0112
-#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS	0x0122
-#define PCI_CHIP_SANDYBRIDGE_M_GT1	0x0106	/* Mobile */
-#define PCI_CHIP_SANDYBRIDGE_M_GT2	0x0116
-#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS	0x0126
-#define PCI_CHIP_SANDYBRIDGE_S		0x010A	/* Server */
-
-#define PCI_CHIP_IVYBRIDGE_GT1          0x0152  /* Desktop */
-#define PCI_CHIP_IVYBRIDGE_GT2          0x0162
-#define PCI_CHIP_IVYBRIDGE_M_GT1        0x0156  /* Mobile */
-#define PCI_CHIP_IVYBRIDGE_M_GT2        0x0166
-#define PCI_CHIP_IVYBRIDGE_S_GT1        0x015a  /* Server */
-
-#define IS_MOBILE(devid)	(devid == PCI_CHIP_I855_GM || \
-				 devid == PCI_CHIP_I915_GM || \
-				 devid == PCI_CHIP_I945_GM || \
-				 devid == PCI_CHIP_I945_GME || \
-				 devid == PCI_CHIP_I965_GM || \
-				 devid == PCI_CHIP_I965_GME || \
-				 devid == PCI_CHIP_GM45_GM || \
-				 IS_IGD(devid) || \
-				 devid == PCI_CHIP_ILM_G)
-
-#define IS_G45(devid)           (devid == PCI_CHIP_IGD_E_G || \
-                                 devid == PCI_CHIP_Q45_G || \
-                                 devid == PCI_CHIP_G45_G || \
-                                 devid == PCI_CHIP_G41_G || \
-                                 devid == PCI_CHIP_B43_G || \
-                                 devid == PCI_CHIP_B43_G1)
-#define IS_GM45(devid)          (devid == PCI_CHIP_GM45_GM)
-#define IS_G4X(devid)		(IS_G45(devid) || IS_GM45(devid))
-
-#define IS_ILD(devid)           (devid == PCI_CHIP_ILD_G)
-#define IS_ILM(devid)           (devid == PCI_CHIP_ILM_G)
-#define IS_GEN5(devid)          (IS_ILD(devid) || IS_ILM(devid))
-
-#define IS_915(devid)		(devid == PCI_CHIP_I915_G || \
-				 devid == PCI_CHIP_E7221_G || \
-				 devid == PCI_CHIP_I915_GM)
-
-#define IS_945(devid)		(devid == PCI_CHIP_I945_G || \
-				 devid == PCI_CHIP_I945_GM || \
-				 devid == PCI_CHIP_I945_GME || \
-				 devid == PCI_CHIP_G33_G || \
-				 devid == PCI_CHIP_Q33_G || \
-				 devid == PCI_CHIP_Q35_G || IS_IGD(devid))
-
-#define IS_GEN4(devid)		(devid == PCI_CHIP_I965_G || \
-				 devid == PCI_CHIP_I965_Q || \
-				 devid == PCI_CHIP_I965_G_1 || \
-				 devid == PCI_CHIP_I965_GM || \
-				 devid == PCI_CHIP_I965_GME || \
-				 devid == PCI_CHIP_I946_GZ || \
-				 IS_G4X(devid))
-
-/* Compat macro for intel_decode.c */
-#define IS_IRONLAKE(devid)	IS_GEN5(devid)
-
-#define IS_SNB_GT1(devid)	(devid == PCI_CHIP_SANDYBRIDGE_GT1 || \
-				 devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
-				 devid == PCI_CHIP_SANDYBRIDGE_S)
-
-#define IS_SNB_GT2(devid)	(devid == PCI_CHIP_SANDYBRIDGE_GT2 || \
-				 devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS	|| \
-				 devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
-				 devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS)
-
-#define IS_GEN6(devid)		(IS_SNB_GT1(devid) || IS_SNB_GT2(devid))
-
-#define IS_IVB_GT1(devid)       (devid == PCI_CHIP_IVYBRIDGE_GT1 || \
-				 devid == PCI_CHIP_IVYBRIDGE_M_GT1 || \
-				 devid == PCI_CHIP_IVYBRIDGE_S_GT1)
-
-#define IS_IVB_GT2(devid)       (devid == PCI_CHIP_IVYBRIDGE_GT2 || \
-				 devid == PCI_CHIP_IVYBRIDGE_M_GT2)
-
-#define IS_IVYBRIDGE(devid)     (IS_IVB_GT1(devid) || IS_IVB_GT2(devid))
-
-#define IS_GEN7(devid)	        IS_IVYBRIDGE(devid)
-
-#define IS_965(devid)		(IS_GEN4(devid) || \
-				 IS_G4X(devid) || \
-				 IS_GEN5(devid) || \
-				 IS_GEN6(devid) || \
-				 IS_GEN7(devid))
-
-#define IS_9XX(devid)		(IS_915(devid) || \
-				 IS_945(devid) || \
-				 IS_965(devid))
-
-#define IS_GEN3(devid)		(IS_915(devid) ||	\
-				 IS_945(devid))
-
-#define IS_GEN2(devid)		(devid == PCI_CHIP_I830_M || \
-				 devid == PCI_CHIP_845_G ||  \
-				 devid == PCI_CHIP_I855_GM ||	\
-				 devid == PCI_CHIP_I865_G)
diff --git a/gralloc_drm_intel.c b/gralloc_drm_intel.c
index 6a0d7e0..649c6ff 100644
--- a/gralloc_drm_intel.c
+++ b/gralloc_drm_intel.c
@@ -489,7 +489,7 @@ static void intel_unmap(struct gralloc_drm_drv_t *drv,
 		drm_intel_bo_unmap(ib->ibo);
 }
 
-#include "dri/intel_chipset.h" /* for IS_965() */
+#include "intel_chipset.h" /* for platform detection macros */
 static void intel_init_kms_features(struct gralloc_drm_drv_t *drv,
 		struct gralloc_drm_t *drm)
 {
@@ -522,8 +522,11 @@ static void intel_init_kms_features(struct gralloc_drm_drv_t *drv,
 	if (drmCommandWriteRead(drm->fd, DRM_I915_GETPARAM, &gp, sizeof(gp)))
 		id = 0;
 
-	if (IS_965(id)) {
-		if (IS_GEN6(id))
+	/* GEN4, G4X, GEN5, GEN6, GEN7 */
+	if ((IS_9XX(id) || IS_G4X(id)) && !IS_GEN3(id)) {
+		if (IS_GEN7(id))
+			info->gen = 70;
+		else if (IS_GEN6(id))
 			info->gen = 60;
 		else if (IS_GEN5(id))
 			info->gen = 50;
diff --git a/pci_ids/i915_pci_ids.h b/pci_ids/i915_pci_ids.h
deleted file mode 100644
index 551c010..0000000
--- a/pci_ids/i915_pci_ids.h
+++ /dev/null
@@ -1,15 +0,0 @@
-CHIPSET(0x3577, I830_M, i8xx)
-CHIPSET(0x2562, 845_G, i8xx)
-CHIPSET(0x3582, I855_GM, i8xx)
-CHIPSET(0x2572, I865_G, i8xx)
-CHIPSET(0x2582, I915_G, i915)
-CHIPSET(0x258A, E7221_G, i915)
-CHIPSET(0x2592, I915_GM, i915)
-CHIPSET(0x2772, I945_G, i945)
-CHIPSET(0x27A2, I945_GM, i945)
-CHIPSET(0x27AE, I945_GME, i945)
-CHIPSET(0x29B2, Q35_G, i945)
-CHIPSET(0x29C2, G33_G, i945)
-CHIPSET(0x29D2, Q33_G, i945)
-CHIPSET(0xA011, IGD_GM, i945)
-CHIPSET(0xA001, IGD_G, i945)
diff --git a/pci_ids/i965_pci_ids.h b/pci_ids/i965_pci_ids.h
deleted file mode 100644
index d37a2ee..0000000
--- a/pci_ids/i965_pci_ids.h
+++ /dev/null
@@ -1,27 +0,0 @@
-CHIPSET(0x29A2, I965_G, i965)
-CHIPSET(0x2992, I965_Q, i965)
-CHIPSET(0x2982, I965_G_1, i965)
-CHIPSET(0x2972, I946_GZ, i965)
-CHIPSET(0x2A02, I965_GM, i965)
-CHIPSET(0x2A12, I965_GME, i965)
-CHIPSET(0x2A42, GM45_GM, g4x)
-CHIPSET(0x2E02, IGD_E_G, g4x)
-CHIPSET(0x2E12, Q45_G, g4x)
-CHIPSET(0x2E22, G45_G, g4x)
-CHIPSET(0x2E32, G41_G, g4x)
-CHIPSET(0x2E42, B43_G, g4x)
-CHIPSET(0x2E92, B43_G1, g4x)
-CHIPSET(0x0042, ILD_G, ilk)
-CHIPSET(0x0046, ILM_G, ilk)
-CHIPSET(0x0102, SANDYBRIDGE_GT1, snb_gt1)
-CHIPSET(0x0112, SANDYBRIDGE_GT2, snb_gt2)
-CHIPSET(0x0122, SANDYBRIDGE_GT2_PLUS, snb_gt2)
-CHIPSET(0x0106, SANDYBRIDGE_M_GT1, snb_gt1)
-CHIPSET(0x0116, SANDYBRIDGE_M_GT2, snb_gt2)
-CHIPSET(0x0126, SANDYBRIDGE_M_GT2_PLUS, snb_gt2)
-CHIPSET(0x010A, SANDYBRIDGE_S, snb_gt1)
-CHIPSET(0x0152, IVYBRIDGE_GT1, ivb_gt1)
-CHIPSET(0x0162, IVYBRIDGE_GT2, ivb_gt2)
-CHIPSET(0x0156, IVYBRIDGE_M_GT1, ivb_gt1)
-CHIPSET(0x0166, IVYBRIDGE_M_GT2, ivb_gt2)
-CHIPSET(0x015a, IVYBRIDGE_S_GT1, ivb_gt1)