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author | Jim Grosbach <grosbach@apple.com> | 2013-03-07 05:47:54 +0000 |
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committer | Jim Grosbach <grosbach@apple.com> | 2013-03-07 05:47:54 +0000 |
commit | 34fd0d2b93edb3ddefe5c5766073273f86b23b78 (patch) | |
tree | 64fbf0c2d59c25afe84b15894fca3367a5069fe0 | |
parent | 218042a02305a3cc38d968a97ff9ecf4b4abe6ff (diff) | |
download | external_llvm-34fd0d2b93edb3ddefe5c5766073273f86b23b78.zip external_llvm-34fd0d2b93edb3ddefe5c5766073273f86b23b78.tar.gz external_llvm-34fd0d2b93edb3ddefe5c5766073273f86b23b78.tar.bz2 |
SDAG: Handle scalarizing an extend of a <1 x iN> vector.
Just scalarize the element and rebuild a vector of the result type
from that.
rdar://13281568
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176614 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeTypes.h | 1 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 20 | ||||
-rw-r--r-- | test/CodeGen/Thumb2/2013-03-06-vector-sext-operand-scalarize.ll | 19 |
3 files changed, 40 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/lib/CodeGen/SelectionDAG/LegalizeTypes.h index 7de42ea..27b3cf2 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeTypes.h +++ b/lib/CodeGen/SelectionDAG/LegalizeTypes.h @@ -530,6 +530,7 @@ private: // Vector Operand Scalarization: <1 x ty> -> ty. bool ScalarizeVectorOperand(SDNode *N, unsigned OpNo); SDValue ScalarizeVecOp_BITCAST(SDNode *N); + SDValue ScalarizeVecOp_EXTEND(SDNode *N); SDValue ScalarizeVecOp_CONCAT_VECTORS(SDNode *N); SDValue ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N); SDValue ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo); diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 09a50d9..5ec8535 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -365,6 +365,11 @@ bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) { case ISD::BITCAST: Res = ScalarizeVecOp_BITCAST(N); break; + case ISD::ANY_EXTEND: + case ISD::ZERO_EXTEND: + case ISD::SIGN_EXTEND: + Res = ScalarizeVecOp_EXTEND(N); + break; case ISD::CONCAT_VECTORS: Res = ScalarizeVecOp_CONCAT_VECTORS(N); break; @@ -400,6 +405,21 @@ SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) { N->getValueType(0), Elt); } +/// ScalarizeVecOp_EXTEND - If the value to extend is a vector that needs +/// to be scalarized, it must be <1 x ty>. Extend the element instead. +SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTEND(SDNode *N) { + assert(N->getValueType(0).getVectorNumElements() == 1 && + "Unexected vector type!"); + SDValue Elt = GetScalarizedVector(N->getOperand(0)); + SmallVector<SDValue, 1> Ops(1); + Ops[0] = DAG.getNode(N->getOpcode(), N->getDebugLoc(), + N->getValueType(0).getScalarType(), Elt); + // Revectorize the result so the types line up with what the uses of this + // expression expect. + return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0), + &Ops[0], 1); +} + /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one - /// use a BUILD_VECTOR instead. SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) { diff --git a/test/CodeGen/Thumb2/2013-03-06-vector-sext-operand-scalarize.ll b/test/CodeGen/Thumb2/2013-03-06-vector-sext-operand-scalarize.ll new file mode 100644 index 0000000..203815f --- /dev/null +++ b/test/CodeGen/Thumb2/2013-03-06-vector-sext-operand-scalarize.ll @@ -0,0 +1,19 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s + +; Testing that these don't crash/assert. The loop vectorizer can end up +; with odd constructs like this. The code actually generated is incidental. +define <1 x i64> @test_zext(i32 %a) nounwind { +; CHECK: test_zext: + %Cmp = icmp uge i32 %a, 42 + %vec = insertelement <1 x i1> zeroinitializer, i1 %Cmp, i32 0 + %Se = zext <1 x i1> %vec to <1 x i64> + ret <1 x i64> %Se +} + +define <1 x i64> @test_sext(i32 %a) nounwind { +; CHECK: test_sext: + %Cmp = icmp uge i32 %a, 42 + %vec = insertelement <1 x i1> zeroinitializer, i1 %Cmp, i32 0 + %Se = sext <1 x i1> %vec to <1 x i64> + ret <1 x i64> %Se +} |