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authorMichael Liao <michael.liao@intel.com>2012-10-17 03:59:18 +0000
committerMichael Liao <michael.liao@intel.com>2012-10-17 03:59:18 +0000
commit35a5640254d38fcdf73b22a839980aaacd437092 (patch)
treec152e0c074a0f13dfaca2b7b22a548816261765b
parent281ae5abf57a4d318d308c0dd1326ff65d540b78 (diff)
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Check SSSE3 instead of SSE4.1
- All shuffle insns required, especially PSHUB, are added in SSSE3. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166086 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/X86/X86ISelLowering.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index fb0fdb3..a205aef 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -15477,11 +15477,11 @@ static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
ISD::LoadExtType Ext = Ld->getExtensionType();
// If this is a vector EXT Load then attempt to optimize it using a
- // shuffle. We need SSE4 for the shuffles.
+ // shuffle. We need SSSE3 shuffles.
// TODO: It is possible to support ZExt by zeroing the undef values
// during the shuffle phase or after the shuffle.
if (RegVT.isVector() && RegVT.isInteger() &&
- Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
+ Ext == ISD::EXTLOAD && Subtarget->hasSSSE3()) {
assert(MemVT != RegVT && "Cannot extend to the same type");
assert(MemVT.isVector() && "Must load a vector from memory");