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authorAaron Ballman <aaron@aaronballman.com>2013-04-03 00:33:32 +0000
committerAaron Ballman <aaron@aaronballman.com>2013-04-03 00:33:32 +0000
commit3b148e5be8ac0683e53793cfa3761b4d84e3eda2 (patch)
tree5b1d6c1e42ac35f4d45fc23d3233e5590db00eab
parent8ec018c67894458ce1d9a34cab8b072e54e0d2c8 (diff)
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This patch addresses PR15351 by explicitly checking for AVX support
when getting the host processor information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178598 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Support/Host.cpp24
1 files changed, 22 insertions, 2 deletions
diff --git a/lib/Support/Host.cpp b/lib/Support/Host.cpp
index b9bbcb9..372b7fc 100644
--- a/lib/Support/Host.cpp
+++ b/lib/Support/Host.cpp
@@ -112,6 +112,18 @@ static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX,
#endif
}
+static bool OSHasAVXSupport() {
+#if defined(__GNUC__)
+ int rEAX, rEDX;
+ __asm__ ("xgetbv" : "=a" (rEAX), "=d" (rEDX) : "c" (0));
+#elif defined(_MSC_VER)
+ unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
+#else
+ int rEAX = 0; // Ensures we return false
+#endif
+ return (rEAX & 6) == 6;
+}
+
static void DetectX86FamilyModel(unsigned EAX, unsigned &Family,
unsigned &Model) {
Family = (EAX >> 8) & 0xf; // Bits 8 - 11
@@ -134,6 +146,10 @@ std::string sys::getHostCPUName() {
DetectX86FamilyModel(EAX, Family, Model);
bool HasSSE3 = (ECX & 0x1);
+ // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
+ // indicates that the AVX registers will be saved and restored on context
+ // switch, when we have full AVX support.
+ bool HasAVX = (ECX & ((1 << 28) | (1 << 27))) != 0 && OSHasAVXSupport();
GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
bool Em64T = (EDX >> 29) & 0x1;
@@ -243,11 +259,15 @@ std::string sys::getHostCPUName() {
case 42: // Intel Core i7 processor. All processors are manufactured
// using the 32 nm process.
case 45:
- return "corei7-avx";
+ // Not all Sandy Bridge processors support AVX (such as the Pentium
+ // versions instead of the i7 versions).
+ return HasAVX ? "corei7-avx" : "corei7";
// Ivy Bridge:
case 58:
- return "core-avx-i";
+ // Not all Ivy Bridge processors support AVX (such as the Pentium
+ // versions instead of the i7 versions).
+ return HasAVX ? "core-avx-i" : "corei7";
case 28: // Most 45 nm Intel Atom processors
case 38: // 45 nm Atom Lincroft