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author | Ying Wang <wangying@google.com> | 2013-02-20 13:30:01 -0800 |
---|---|---|
committer | Ying Wang <wangying@google.com> | 2013-02-20 13:35:19 -0800 |
commit | 45c4ebb169e5d37560b1a3ef27148eb125cd6701 (patch) | |
tree | 8247ce393b5d5100df3b85affc8ee85b1809642c | |
parent | fbe6c40c6744c36ef90937b5127e0d9259b6fcd7 (diff) | |
download | external_llvm-45c4ebb169e5d37560b1a3ef27148eb125cd6701.zip external_llvm-45c4ebb169e5d37560b1a3ef27148eb125cd6701.tar.gz external_llvm-45c4ebb169e5d37560b1a3ef27148eb125cd6701.tar.bz2 |
Use order-only dependency on $(TBLGEN).
So if the tblgen binary is updated we dont run the rules again.
Bug: 8234097
Change-Id: Ia31a137e2bde8fd750d52596a8e5b8def9a2d87d
-rw-r--r-- | llvm-gen-intrinsics.mk | 2 | ||||
-rw-r--r-- | llvm-tblgen-rules.mk | 50 |
2 files changed, 26 insertions, 26 deletions
diff --git a/llvm-gen-intrinsics.mk b/llvm-gen-intrinsics.mk index 3a97717..bae748e 100644 --- a/llvm-gen-intrinsics.mk +++ b/llvm-gen-intrinsics.mk @@ -11,7 +11,7 @@ endif GENFILE := $(addprefix $(call local-intermediates-dir)/llvm/IR/,Intrinsics.gen) LOCAL_GENERATED_SOURCES += $(GENFILE) $(GENFILE): TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) -$(GENFILE): $(INTRINSICTD) $(INTRINSICTDS) $(TBLGEN) +$(GENFILE): $(INTRINSICTD) $(INTRINSICTDS) | $(TBLGEN) ifeq ($(LOCAL_IS_HOST_MODULE),true) $(call transform-host-td-to-out,intrinsic) else diff --git a/llvm-tblgen-rules.mk b/llvm-tblgen-rules.mk index ddcac23..e3a7ca3 100644 --- a/llvm-tblgen-rules.mk +++ b/llvm-tblgen-rules.mk @@ -41,51 +41,51 @@ tblgen_td_deps := $(wildcard $(tblgen_td_deps)) ifeq ($(tblgen_source_dir),$(LLVM_ROOT_PATH)/lib/Target/ARM/MCTargetDesc) $(intermediates)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \ - $(tblgen_td_deps) $(TBLGEN) + $(tblgen_td_deps) | $(TBLGEN) $(call transform-td-to-out, register-info) $(intermediates)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \ - $(tblgen_td_deps) $(TBLGEN) + $(tblgen_td_deps) | $(TBLGEN) $(call transform-td-to-out,instr-info) $(intermediates)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \ - $(tblgen_td_deps) $(TBLGEN) + $(tblgen_td_deps) | $(TBLGEN) $(call transform-td-to-out,subtarget) endif ifeq ($(tblgen_source_dir),$(LLVM_ROOT_PATH)/lib/Target/X86/MCTargetDesc) $(intermediates)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \ - $(tblgen_td_deps) $(TBLGEN) + $(tblgen_td_deps) | $(TBLGEN) $(call transform-td-to-out, register-info) $(intermediates)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \ - $(tblgen_td_deps) $(TBLGEN) + $(tblgen_td_deps) | $(TBLGEN) $(call transform-td-to-out,instr-info) $(intermediates)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \ - $(tblgen_td_deps) $(TBLGEN) + $(tblgen_td_deps) | $(TBLGEN) $(call transform-td-to-out,subtarget) endif ifeq ($(tblgen_source_dir),$(LLVM_ROOT_PATH)/lib/Target/Mips/MCTargetDesc) $(intermediates)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenRegisterInfo.inc: $(tblgen_source_dir)/../%.td \ - $(tblgen_td_deps) $(TBLGEN) + $(tblgen_td_deps) | $(TBLGEN) $(call transform-td-to-out, register-info) $(intermediates)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenInstrInfo.inc: $(tblgen_source_dir)/../%.td \ - $(tblgen_td_deps) $(TBLGEN) + $(tblgen_td_deps) | $(TBLGEN) $(call transform-td-to-out,instr-info) $(intermediates)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/../%.td \ - $(tblgen_td_deps) $(TBLGEN) + $(tblgen_td_deps) | $(TBLGEN) $(call transform-td-to-out,subtarget) endif @@ -93,112 +93,112 @@ endif ifneq ($(filter %GenRegisterInfo.inc,$(tblgen_gen_tables)),) $(intermediates)/%GenRegisterInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenRegisterInfo.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) $(TBLGEN) + $(tblgen_td_deps) | $(TBLGEN) $(call transform-td-to-out,register-info) endif ifneq ($(filter %GenInstrInfo.inc,$(tblgen_gen_tables)),) $(intermediates)/%GenInstrInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenInstrInfo.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) $(TBLGEN) + $(tblgen_td_deps) | $(TBLGEN) $(call transform-td-to-out,instr-info) endif ifneq ($(filter %GenAsmWriter.inc,$(tblgen_gen_tables)),) $(intermediates)/%GenAsmWriter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenAsmWriter.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) $(TBLGEN) + $(tblgen_td_deps) | $(TBLGEN) $(call transform-td-to-out,asm-writer) endif ifneq ($(filter %GenAsmWriter1.inc,$(tblgen_gen_tables)),) $(intermediates)/%GenAsmWriter1.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenAsmWriter1.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) $(TBLGEN) + $(tblgen_td_deps) | $(TBLGEN) $(call transform-td-to-out,asm-writer -asmwriternum=1) endif ifneq ($(filter %GenAsmMatcher.inc,$(tblgen_gen_tables)),) $(intermediates)/%GenAsmMatcher.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenAsmMatcher.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) $(TBLGEN) + $(tblgen_td_deps) | $(TBLGEN) $(call transform-td-to-out,asm-matcher) endif ifneq ($(filter %GenCodeEmitter.inc,$(tblgen_gen_tables)),) $(intermediates)/%GenCodeEmitter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenCodeEmitter.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) $(TBLGEN) + $(tblgen_td_deps) | $(TBLGEN) $(call transform-td-to-out,emitter) endif ifneq ($(filter %GenMCCodeEmitter.inc,$(tblgen_gen_tables)),) $(intermediates)/%GenMCCodeEmitter.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenMCCodeEmitter.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) $(TBLGEN) + $(tblgen_td_deps) | $(TBLGEN) $(call transform-td-to-out,emitter -mc-emitter) endif ifneq ($(filter %GenMCPseudoLowering.inc,$(tblgen_gen_tables)),) $(intermediates)/%GenMCPseudoLowering.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenMCPseudoLowering.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) $(TBLGEN) + $(tblgen_td_deps) | $(TBLGEN) $(call transform-td-to-out,pseudo-lowering) endif ifneq ($(filter %GenDAGISel.inc,$(tblgen_gen_tables)),) $(intermediates)/%GenDAGISel.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenDAGISel.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) $(TBLGEN) + $(tblgen_td_deps) | $(TBLGEN) $(call transform-td-to-out,dag-isel) endif ifneq ($(filter %GenDisassemblerTables.inc,$(tblgen_gen_tables)),) $(intermediates)/%GenDisassemblerTables.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenDisassemblerTables.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) $(TBLGEN) + $(tblgen_td_deps) | $(TBLGEN) $(call transform-td-to-out,disassembler) endif ifneq ($(filter %GenEDInfo.inc,$(tblgen_gen_tables)),) $(intermediates)/%GenEDInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenEDInfo.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) $(TBLGEN) + $(tblgen_td_deps) | $(TBLGEN) $(call transform-td-to-out,enhanced-disassembly-info) endif ifneq ($(filter %GenFastISel.inc,$(tblgen_gen_tables)),) $(intermediates)/%GenFastISel.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenFastISel.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) $(TBLGEN) + $(tblgen_td_deps) | $(TBLGEN) $(call transform-td-to-out,fast-isel) endif ifneq ($(filter %GenSubtargetInfo.inc,$(tblgen_gen_tables)),) $(intermediates)/%GenSubtargetInfo.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) $(TBLGEN) + $(tblgen_td_deps) | $(TBLGEN) $(call transform-td-to-out,subtarget) endif ifneq ($(filter %GenCallingConv.inc,$(tblgen_gen_tables)),) $(intermediates)/%GenCallingConv.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenCallingConv.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) $(TBLGEN) + $(tblgen_td_deps) | $(TBLGEN) $(call transform-td-to-out,callingconv) endif ifneq ($(filter %GenIntrinsics.inc,$(tblgen_gen_tables)),) $(intermediates)/%GenIntrinsics.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/%GenIntrinsics.inc: $(tblgen_source_dir)/%.td \ - $(tblgen_td_deps) $(TBLGEN) + $(tblgen_td_deps) | $(TBLGEN) $(call transform-td-to-out,tgt_intrinsics) endif ifneq ($(findstring ARMGenDecoderTables.inc,$(tblgen_gen_tables)),) $(intermediates)/ARMGenDecoderTables.inc: TBLGEN_LOCAL_MODULE := $(LOCAL_MODULE) $(intermediates)/ARMGenDecoderTables.inc: $(tblgen_source_dir)/ARM.td \ - $(tblgen_td_deps) $(TBLGEN) + $(tblgen_td_deps) | $(TBLGEN) $(call transform-td-to-out,arm-decoder) endif |