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authorRuchira Sasanka <sasanka@students.uiuc.edu>2001-10-23 21:40:39 +0000
committerRuchira Sasanka <sasanka@students.uiuc.edu>2001-10-23 21:40:39 +0000
commit88dedc1544a5c7235b49b4d9b14f8beeb95317e2 (patch)
tree4a80974480aaf6f55bc210b00a15bfecacf040bf
parentf7434f0e1d1b7f711d13749efeea18a5f364eeb5 (diff)
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Corrected a bug in SparcRegInfo.cpp - to add inserted instructions before a return
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@969 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/SparcV9/SparcV9RegClassInfo.h2
-rw-r--r--lib/Target/SparcV9/SparcV9RegInfo.cpp31
2 files changed, 16 insertions, 17 deletions
diff --git a/lib/Target/SparcV9/SparcV9RegClassInfo.h b/lib/Target/SparcV9/SparcV9RegClassInfo.h
index 311d035..4f91268 100644
--- a/lib/Target/SparcV9/SparcV9RegClassInfo.h
+++ b/lib/Target/SparcV9/SparcV9RegClassInfo.h
@@ -66,7 +66,7 @@ class SparcIntRegOrder{
};
// max # of colors reg coloring can allocate
- static unsigned int const NumOfAvailRegs = g0;
+ static unsigned int const NumOfAvailRegs = i6;
static unsigned int const StartOfNonVolatileRegs = l0;
static unsigned int const StartOfAllRegs = o0;
diff --git a/lib/Target/SparcV9/SparcV9RegInfo.cpp b/lib/Target/SparcV9/SparcV9RegInfo.cpp
index b28ce51..0f3f9dc 100644
--- a/lib/Target/SparcV9/SparcV9RegInfo.cpp
+++ b/lib/Target/SparcV9/SparcV9RegInfo.cpp
@@ -621,8 +621,7 @@ void UltraSparcRegInfo::suggestReg4RetValue(const MachineInstr *const RetMI,
assert( (UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode() ) );
-
- suggestReg4RetAddr(RetMI, LRI);
+ suggestReg4RetAddr(RetMI, LRI);
// if there is an implicit ref, that has to be the ret value
if( RetMI->getNumImplicitRefs() > 0 ) {
@@ -681,37 +680,37 @@ void UltraSparcRegInfo::colorRetValue(const MachineInstr *const RetMI,
unsigned RegClassID = getRegClassIDOfValue(RetVal);
unsigned RegType = getRegType( RetVal );
- unsigned UniRetReg = InvalidRegNum;
-
+
+
+ unsigned CorrectCol;
if(RegClassID == IntRegClassID)
- UniRetReg = getUnifiedRegNum( RegClassID, SparcIntRegOrder::i0 );
+ CorrectCol = SparcIntRegOrder::i0;
else if(RegClassID == FloatRegClassID)
- UniRetReg = getUnifiedRegNum( RegClassID, SparcFloatRegOrder::f0);
-
+ CorrectCol = SparcFloatRegOrder::f0;
+ else
+ assert( 0 && "Unknown RegClass");
// if the LR received the suggested color, NOTHING to do
if( LR->hasSuggestedColor() && LR->hasColor() )
if( LR->getSuggestedColor() == LR->getColor() )
- return;
+ if( LR->getColor() == CorrectCol )
+ return;
+
+ unsigned UniRetReg = getUnifiedRegNum( RegClassID, CorrectCol );
if( LR->hasColor() ) {
- // We are here because the LR was allocted a regiter, but NOT
- // the correct register.
+ // We are here because the LR was allocted a regiter
+ // It may be the suggested register or not
// copy the LR of retun value to i0 or f0
unsigned UniLRReg =getUnifiedRegNum( RegClassID, LR->getColor());
- if(RegClassID == IntRegClassID)
- UniRetReg = getUnifiedRegNum( RegClassID, SparcIntRegOrder::i0);
- else if(RegClassID == FloatRegClassID)
- UniRetReg = getUnifiedRegNum( RegClassID, SparcFloatRegOrder::f0);
-
AdMI = cpReg2RegMI( UniLRReg, UniRetReg, RegType);
-
+ RetAI->InstrnsBefore.push_back( AdMI );
}
else
assert(0 && "TODO: Copy the return value from stack\n");