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authorBenjamin Kramer <benny.kra@googlemail.com>2012-02-28 18:37:06 +0000
committerBenjamin Kramer <benny.kra@googlemail.com>2012-02-28 18:37:06 +0000
commita3b2121ccf4f048640b4d79689b0e4a3906143f2 (patch)
tree2c4c484a5c53ce53693920bc11389559307c2446
parent21a1401413f074ffb216f74f94c5bc7a0e6cc1e1 (diff)
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Fix off-by one in comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151644 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 38467c5..348dc5d 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1402,7 +1402,7 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
if ((KnownZero & HighBitMask) == HighBitMask) {
// Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
// shift if x is zero. We can use XOR here because x is known to be smaller
- // than 31.
+ // than 32.
SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
DAG.getConstant(NVTBits-1, ShTy));