diff options
| author | Cedric Venet <cedric.venet@laposte.net> | 2008-08-24 11:56:40 +0000 |
|---|---|---|
| committer | Cedric Venet <cedric.venet@laposte.net> | 2008-08-24 11:56:40 +0000 |
| commit | a3f343f4cd453b33214ba892bfeb58706fcf8cea (patch) | |
| tree | 25c144763dfb52ceb95346480eb2e8dfefd6b4dc | |
| parent | 01571ef1e9d58ad097c61226d2f81426d048e287 (diff) | |
| download | external_llvm-a3f343f4cd453b33214ba892bfeb58706fcf8cea.zip external_llvm-a3f343f4cd453b33214ba892bfeb58706fcf8cea.tar.gz external_llvm-a3f343f4cd453b33214ba892bfeb58706fcf8cea.tar.bz2 | |
Updating VC++ project.
Adding one include file and correct one declaration from class to struct in order to make llvm compile on VC2005.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55279 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | include/llvm/Value.h | 2 | ||||
| -rw-r--r-- | lib/Support/raw_ostream.cpp | 1 | ||||
| -rw-r--r-- | win32/CodeGen/CodeGen.vcproj | 34 | ||||
| -rw-r--r-- | win32/Transforms/Transforms.vcproj | 4 | ||||
| -rw-r--r-- | win32/x86/x86.vcproj | 28 |
5 files changed, 43 insertions, 26 deletions
diff --git a/include/llvm/Value.h b/include/llvm/Value.h index ceb1ad2..b86d137 100644 --- a/include/llvm/Value.h +++ b/include/llvm/Value.h @@ -36,7 +36,7 @@ class TypeSymbolTable; template<typename ValueTy> class StringMapEntry; typedef StringMapEntry<Value*> ValueName; class raw_ostream; -class AssemblyAnnotationWriter; +struct AssemblyAnnotationWriter; //===----------------------------------------------------------------------===// // Value Class diff --git a/lib/Support/raw_ostream.cpp b/lib/Support/raw_ostream.cpp index b9beac2..008f856 100644 --- a/lib/Support/raw_ostream.cpp +++ b/lib/Support/raw_ostream.cpp @@ -26,6 +26,7 @@ #if defined(_MSC_VER) #include <io.h> +#include <fcntl.h> #ifndef STDIN_FILENO # define STDIN_FILENO 0 #endif diff --git a/win32/CodeGen/CodeGen.vcproj b/win32/CodeGen/CodeGen.vcproj index 47855c6..37ba872 100644 --- a/win32/CodeGen/CodeGen.vcproj +++ b/win32/CodeGen/CodeGen.vcproj @@ -89,11 +89,11 @@ /> </Configuration> <Configuration - Name="Debug|x64" + Name="Release|Win32" OutputDirectory="$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)" IntermediateDirectory="$(PlatformName)\$(ConfigurationName)" ConfigurationType="4" - InheritedPropertySheets="$(VCInstallDir)VCProjectDefaults\UpgradeFromVC71.vsprops" + InheritedPropertySheets="$(VCInstallDir)VCProjectDefaults\UpgradeFromVC71.vsprops;..\common.vsprops" CharacterSet="2" > <Tool @@ -110,22 +110,17 @@ /> <Tool Name="VCMIDLTool" - TargetEnvironment="3" /> <Tool Name="VCCLCompilerTool" - Optimization="0" AdditionalIncludeDirectories="..\..\include;.." - PreprocessorDefinitions="_CRT_SECURE_NO_DEPRECATE;_CRT_SECURE_NO_WARNINGS;_SCL_SECURE_NO_WARNINGS;_CRT_NONSTDC_NO_WARNINGS;WIN32;_DEBUG;_LIB;__STDC_LIMIT_MACROS" + PreprocessorDefinitions="_CRT_SECURE_NO_DEPRECATE;_CRT_SECURE_NO_WARNINGS;_SCL_SECURE_NO_WARNINGS;_CRT_NONSTDC_NO_WARNINGS;WIN32;NDEBUG;_LIB;__STDC_LIMIT_MACROS" StringPooling="true" - MinimalRebuild="true" - BasicRuntimeChecks="3" - RuntimeLibrary="3" + RuntimeLibrary="2" ForceConformanceInForLoopScope="true" RuntimeTypeInfo="true" UsePrecompiledHeader="0" ProgramDataBaseFileName="$(OutDir)\$(ProjectName).pdb" - BrowseInformation="1" WarningLevel="3" Detect64BitPortabilityProblems="false" DebugInformationFormat="3" @@ -161,11 +156,11 @@ /> </Configuration> <Configuration - Name="Release|Win32" + Name="Debug|x64" OutputDirectory="$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)" IntermediateDirectory="$(PlatformName)\$(ConfigurationName)" ConfigurationType="4" - InheritedPropertySheets="$(VCInstallDir)VCProjectDefaults\UpgradeFromVC71.vsprops;..\common.vsprops" + InheritedPropertySheets="$(VCInstallDir)VCProjectDefaults\UpgradeFromVC71.vsprops" CharacterSet="2" > <Tool @@ -182,17 +177,22 @@ /> <Tool Name="VCMIDLTool" + TargetEnvironment="3" /> <Tool Name="VCCLCompilerTool" + Optimization="0" AdditionalIncludeDirectories="..\..\include;.." - PreprocessorDefinitions="_CRT_SECURE_NO_DEPRECATE;_CRT_SECURE_NO_WARNINGS;_SCL_SECURE_NO_WARNINGS;_CRT_NONSTDC_NO_WARNINGS;WIN32;NDEBUG;_LIB;__STDC_LIMIT_MACROS" + PreprocessorDefinitions="_CRT_SECURE_NO_DEPRECATE;_CRT_SECURE_NO_WARNINGS;_SCL_SECURE_NO_WARNINGS;_CRT_NONSTDC_NO_WARNINGS;WIN32;_DEBUG;_LIB;__STDC_LIMIT_MACROS" StringPooling="true" - RuntimeLibrary="2" + MinimalRebuild="true" + BasicRuntimeChecks="3" + RuntimeLibrary="3" ForceConformanceInForLoopScope="true" RuntimeTypeInfo="true" UsePrecompiledHeader="0" ProgramDataBaseFileName="$(OutDir)\$(ProjectName).pdb" + BrowseInformation="1" WarningLevel="3" Detect64BitPortabilityProblems="false" DebugInformationFormat="3" @@ -504,6 +504,10 @@ > </File> <File + RelativePath="..\..\lib\CodeGen\SelectionDAG\FastISel.cpp" + > + </File> + <File RelativePath="..\..\lib\CodeGen\SelectionDAG\LegalizeDAG.cpp" > </File> @@ -552,10 +556,6 @@ > </File> <File - RelativePath="..\..\lib\CodeGen\SelectionDAG\SimpleBBISel.cpp" - > - </File> - <File RelativePath="..\..\lib\CodeGen\SelectionDAG\TargetLowering.cpp" > </File> diff --git a/win32/Transforms/Transforms.vcproj b/win32/Transforms/Transforms.vcproj index ef57d43..101c04e 100644 --- a/win32/Transforms/Transforms.vcproj +++ b/win32/Transforms/Transforms.vcproj @@ -602,6 +602,10 @@ > </File> <File + RelativePath="..\..\lib\Transforms\Utils\InstructionNamer.cpp" + > + </File> + <File RelativePath="..\..\lib\Transforms\Utils\LCSSA.cpp" > </File> diff --git a/win32/x86/x86.vcproj b/win32/x86/x86.vcproj index 7880174..57cd1b7 100644 --- a/win32/x86/x86.vcproj +++ b/win32/x86/x86.vcproj @@ -314,9 +314,9 @@ <Tool Name="VCCustomBuildTool" Description="Performing TableGen Step" - CommandLine="echo Building $(InputFileName) register names with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-register-enums -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenRegisterNames.inc
echo Building $(InputFileName) register information header with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-register-desc-header -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenRegisterInfo.h.inc
echo Building $(InputFileName) register information implementation with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-register-desc -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenRegisterInfo.inc
echo Building $(InputFileName) instruction names with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-instr-enums -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenInstrNames.inc
echo Building $(InputFileName) instruction information with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-instr-desc -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenInstrInfo.inc
echo Building $(InputFileName) assembly writer with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-asm-writer -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenAsmWriter.inc
echo Building $(InputFileName) assembly writer #1 with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-asm-writer -asmwriternum=1 -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenAsmWriter1.inc
echo Building $(InputFileName) instruction selector implementation with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-dag-isel -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenDAGISel.inc
echo Building $(InputFileName) subtarget information with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-subtarget -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenSubtarget.inc
echo Building $(InputFileName) calling convention information with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-callingconv -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenCallingConv.inc
" + CommandLine="echo Building $(InputFileName) register names with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-register-enums -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenRegisterNames.inc
echo Building $(InputFileName) register information header with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-register-desc-header -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenRegisterInfo.h.inc
echo Building $(InputFileName) register information implementation with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-register-desc -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenRegisterInfo.inc
echo Building $(InputFileName) instruction names with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-instr-enums -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenInstrNames.inc
echo Building $(InputFileName) instruction information with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-instr-desc -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenInstrInfo.inc
echo Building $(InputFileName) assembly writer with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-asm-writer -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenAsmWriter.inc
echo Building $(InputFileName) assembly writer #1 with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-asm-writer -asmwriternum=1 -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenAsmWriter1.inc
echo Building $(InputFileName) instruction selector implementation with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-dag-isel -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenDAGISel.inc
echo Building $(InputFileName) subtarget information with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-subtarget -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenSubtarget.inc
echo Building $(InputFileName) calling convention information with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-callingconv -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenCallingConv.inc
echo Building $(InputFileName) Fast instruction selection with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-fast-isel -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenFastISel.inc
" AdditionalDependencies="$(InputDir)X86InstrInfo.td;$(InputDir)X86RegisterInfo.td;$(InputDir)X86InstrFPStack.td;$(InputDir)X86InstrMMX.td;$(InputDir)X86InstrSSE.td;$(InputDir)X86CallingConv.td;$(InputDir)..\Target.td;$(InputDir)..\TargetSchedule.td;$(InputDir)..\TargetScheduleDAG.td;$(ProjectDir)..\$(IntDir)\TableGen.exe" - Outputs="X86GenRegisterNames.inc;X86GenRegisterInfo.h.inc;X86GenRegisterInfo.inc;X86GenInstrNames.inc;X86GenInstrInfo.inc;X86GenAsmWriter.inc;X86GenAsmWriter1.inc;X86GenDAGISel.inc;X86GenSubtarget.inc;X86GenCallingConv.inc" + Outputs="X86GenRegisterNames.inc;X86GenRegisterInfo.h.inc;X86GenRegisterInfo.inc;X86GenInstrNames.inc;X86GenInstrInfo.inc;X86GenAsmWriter.inc;X86GenAsmWriter1.inc;X86GenDAGISel.inc;X86GenSubtarget.inc;X86GenCallingConv.inc;X86GenFastISel.inc" /> </FileConfiguration> <FileConfiguration @@ -325,9 +325,9 @@ <Tool Name="VCCustomBuildTool" Description="Performing TableGen Step" - CommandLine="echo Building $(InputFileName) register names with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-register-enums -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenRegisterNames.inc
echo Building $(InputFileName) register information header with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-register-desc-header -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenRegisterInfo.h.inc
echo Building $(InputFileName) register information implementation with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-register-desc -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenRegisterInfo.inc
echo Building $(InputFileName) instruction names with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-instr-enums -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenInstrNames.inc
echo Building $(InputFileName) instruction information with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-instr-desc -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenInstrInfo.inc
echo Building $(InputFileName) assembly writer with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-asm-writer -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenAsmWriter.inc
echo Building $(InputFileName) assembly writer #1 with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-asm-writer -asmwriternum=1 -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenAsmWriter1.inc
echo Building $(InputFileName) instruction selector implementation with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-dag-isel -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenDAGISel.inc
echo Building $(InputFileName) subtarget information with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-subtarget -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenSubtarget.inc
echo Building $(InputFileName) calling convention information with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-callingconv -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenCallingConv.inc
" + CommandLine="echo Building $(InputFileName) register names with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-register-enums -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenRegisterNames.inc
echo Building $(InputFileName) register information header with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-register-desc-header -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenRegisterInfo.h.inc
echo Building $(InputFileName) register information implementation with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-register-desc -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenRegisterInfo.inc
echo Building $(InputFileName) instruction names with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-instr-enums -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenInstrNames.inc
echo Building $(InputFileName) instruction information with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-instr-desc -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenInstrInfo.inc
echo Building $(InputFileName) assembly writer with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-asm-writer -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenAsmWriter.inc
echo Building $(InputFileName) assembly writer #1 with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-asm-writer -asmwriternum=1 -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenAsmWriter1.inc
echo Building $(InputFileName) instruction selector implementation with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-dag-isel -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenDAGISel.inc
echo Building $(InputFileName) subtarget information with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-subtarget -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenSubtarget.inc
echo Building $(InputFileName) calling convention information with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-callingconv -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenCallingConv.inc
echo Building $(InputFileName) Fast instruction selection with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-fast-isel -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenFastISel.inc
" AdditionalDependencies="$(InputDir)X86InstrInfo.td;$(InputDir)X86RegisterInfo.td;$(InputDir)X86InstrFPStack.td;$(InputDir)X86InstrMMX.td;$(InputDir)X86InstrSSE.td;$(InputDir)X86CallingConv.td;$(InputDir)..\Target.td;$(InputDir)..\TargetSchedule.td;$(InputDir)..\TargetScheduleDAG.td;$(ProjectDir)..\$(IntDir)\TableGen.exe" - Outputs="X86GenRegisterNames.inc;X86GenRegisterInfo.h.inc;X86GenRegisterInfo.inc;X86GenInstrNames.inc;X86GenInstrInfo.inc;X86GenAsmWriter.inc;X86GenAsmWriter1.inc;X86GenDAGISel.inc;X86GenSubtarget.inc;X86GenCallingConv.inc" + Outputs="X86GenRegisterNames.inc;X86GenRegisterInfo.h.inc;X86GenRegisterInfo.inc;X86GenInstrNames.inc;X86GenInstrInfo.inc;X86GenAsmWriter.inc;X86GenAsmWriter1.inc;X86GenDAGISel.inc;X86GenSubtarget.inc;X86GenCallingConv.inc;X86GenFastISel.inc" /> </FileConfiguration> <FileConfiguration @@ -336,9 +336,9 @@ <Tool Name="VCCustomBuildTool" Description="Performing TableGen Step" - CommandLine="echo Building $(InputFileName) register names with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-register-enums -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenRegisterNames.inc
echo Building $(InputFileName) register information header with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-register-desc-header -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenRegisterInfo.h.inc
echo Building $(InputFileName) register information implementation with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-register-desc -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenRegisterInfo.inc
echo Building $(InputFileName) instruction names with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-instr-enums -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenInstrNames.inc
echo Building $(InputFileName) instruction information with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-instr-desc -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenInstrInfo.inc
echo Building $(InputFileName) assembly writer with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-asm-writer -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenAsmWriter.inc
echo Building $(InputFileName) assembly writer #1 with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-asm-writer -asmwriternum=1 -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenAsmWriter1.inc
echo Building $(InputFileName) instruction selector implementation with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-dag-isel -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenDAGISel.inc
echo Building $(InputFileName) subtarget information with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-subtarget -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenSubtarget.inc
echo Building $(InputFileName) calling convention information with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-callingconv -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenCallingConv.inc
" + CommandLine="echo Building $(InputFileName) register names with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-register-enums -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenRegisterNames.inc
echo Building $(InputFileName) register information header with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-register-desc-header -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenRegisterInfo.h.inc
echo Building $(InputFileName) register information implementation with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-register-desc -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenRegisterInfo.inc
echo Building $(InputFileName) instruction names with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-instr-enums -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenInstrNames.inc
echo Building $(InputFileName) instruction information with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-instr-desc -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenInstrInfo.inc
echo Building $(InputFileName) assembly writer with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-asm-writer -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenAsmWriter.inc
echo Building $(InputFileName) assembly writer #1 with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-asm-writer -asmwriternum=1 -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenAsmWriter1.inc
echo Building $(InputFileName) instruction selector implementation with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-dag-isel -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenDAGISel.inc
echo Building $(InputFileName) subtarget information with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-subtarget -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenSubtarget.inc
echo Building $(InputFileName) calling convention information with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-callingconv -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenCallingConv.inc
echo Building $(InputFileName) Fast instruction selection with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-fast-isel -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenFastISel.inc
" AdditionalDependencies="$(InputDir)X86InstrInfo.td;$(InputDir)X86RegisterInfo.td;$(InputDir)X86InstrFPStack.td;$(InputDir)X86InstrMMX.td;$(InputDir)X86InstrSSE.td;$(InputDir)X86CallingConv.td;$(InputDir)..\Target.td;$(InputDir)..\TargetSchedule.td;$(InputDir)..\TargetScheduleDAG.td;$(ProjectDir)..\$(IntDir)\TableGen.exe" - Outputs="X86GenRegisterNames.inc;X86GenRegisterInfo.h.inc;X86GenRegisterInfo.inc;X86GenInstrNames.inc;X86GenInstrInfo.inc;X86GenAsmWriter.inc;X86GenAsmWriter1.inc;X86GenDAGISel.inc;X86GenSubtarget.inc;X86GenCallingConv.inc" + Outputs="X86GenRegisterNames.inc;X86GenRegisterInfo.h.inc;X86GenRegisterInfo.inc;X86GenInstrNames.inc;X86GenInstrInfo.inc;X86GenAsmWriter.inc;X86GenAsmWriter1.inc;X86GenDAGISel.inc;X86GenSubtarget.inc;X86GenCallingConv.inc;X86GenFastISel.inc" /> </FileConfiguration> <FileConfiguration @@ -347,9 +347,9 @@ <Tool Name="VCCustomBuildTool" Description="Performing TableGen Step" - CommandLine="echo Building $(InputFileName) register names with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-register-enums -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenRegisterNames.inc
echo Building $(InputFileName) register information header with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-register-desc-header -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenRegisterInfo.h.inc
echo Building $(InputFileName) register information implementation with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-register-desc -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenRegisterInfo.inc
echo Building $(InputFileName) instruction names with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-instr-enums -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenInstrNames.inc
echo Building $(InputFileName) instruction information with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-instr-desc -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenInstrInfo.inc
echo Building $(InputFileName) assembly writer with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-asm-writer -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenAsmWriter.inc
echo Building $(InputFileName) assembly writer #1 with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-asm-writer -asmwriternum=1 -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenAsmWriter1.inc
echo Building $(InputFileName) instruction selector implementation with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-dag-isel -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenDAGISel.inc
echo Building $(InputFileName) subtarget information with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-subtarget -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenSubtarget.inc
echo Building $(InputFileName) calling convention information with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-callingconv -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenCallingConv.inc
" + CommandLine="echo Building $(InputFileName) register names with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-register-enums -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenRegisterNames.inc
echo Building $(InputFileName) register information header with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-register-desc-header -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenRegisterInfo.h.inc
echo Building $(InputFileName) register information implementation with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-register-desc -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenRegisterInfo.inc
echo Building $(InputFileName) instruction names with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-instr-enums -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenInstrNames.inc
echo Building $(InputFileName) instruction information with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-instr-desc -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenInstrInfo.inc
echo Building $(InputFileName) assembly writer with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-asm-writer -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenAsmWriter.inc
echo Building $(InputFileName) assembly writer #1 with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-asm-writer -asmwriternum=1 -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenAsmWriter1.inc
echo Building $(InputFileName) instruction selector implementation with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-dag-isel -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenDAGISel.inc
echo Building $(InputFileName) subtarget information with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-subtarget -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenSubtarget.inc
echo Building $(InputFileName) calling convention information with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-callingconv -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenCallingConv.inc
echo Building $(InputFileName) Fast instruction selection with tblgen
$(ProjectDir)..\bin\$(PlatformName)\$(ConfigurationName)\TableGen.exe -gen-fast-isel -I ..\..\lib\Target -I ..\..\lib\Target\X86 -I ..\..\include $(InputPath) -o X86GenFastISel.inc
" AdditionalDependencies="$(InputDir)X86InstrInfo.td;$(InputDir)X86RegisterInfo.td;$(InputDir)X86InstrFPStack.td;$(InputDir)X86InstrMMX.td;$(InputDir)X86InstrSSE.td;$(InputDir)X86CallingConv.td;$(InputDir)..\Target.td;$(InputDir)..\TargetSchedule.td;$(InputDir)..\TargetScheduleDAG.td;$(ProjectDir)..\$(IntDir)\TableGen.exe" - Outputs="X86GenRegisterNames.inc;X86GenRegisterInfo.h.inc;X86GenRegisterInfo.inc;X86GenInstrNames.inc;X86GenInstrInfo.inc;X86GenAsmWriter.inc;X86GenAsmWriter1.inc;X86GenDAGISel.inc;X86GenSubtarget.inc;X86GenCallingConv.inc" + Outputs="X86GenRegisterNames.inc;X86GenRegisterInfo.h.inc;X86GenRegisterInfo.inc;X86GenInstrNames.inc;X86GenInstrInfo.inc;X86GenAsmWriter.inc;X86GenAsmWriter1.inc;X86GenDAGISel.inc;X86GenSubtarget.inc;X86GenCallingConv.inc;X86GenFastISel.inc" /> </FileConfiguration> </File> @@ -392,6 +392,14 @@ > </File> <File + RelativePath="..\..\lib\Target\X86\X86FastISel.cpp" + > + </File> + <File + RelativePath="..\..\lib\Target\X86\X86FastISel.h" + > + </File> + <File RelativePath="..\..\lib\Target\X86\X86FloatingPoint.cpp" > </File> @@ -558,6 +566,10 @@ Name="Generated Tablegen Files" > <File + RelativePath=".\X86GenFastISel.inc" + > + </File> + <File RelativePath=".\X86GenAsmWriter.inc" > </File> |