diff options
| author | Nadav Rotem <nadav.rotem@intel.com> | 2012-05-10 12:39:13 +0000 |
|---|---|---|
| committer | Nadav Rotem <nadav.rotem@intel.com> | 2012-05-10 12:39:13 +0000 |
| commit | b210651654e64bec5eb14214a61da52c451a4044 (patch) | |
| tree | 785df5e0fd42e793827e7ccf07ba63a5f84bfb2c | |
| parent | 5fc2187a025bb77b9023239edf12868d833630fe (diff) | |
| download | external_llvm-b210651654e64bec5eb14214a61da52c451a4044.zip external_llvm-b210651654e64bec5eb14214a61da52c451a4044.tar.gz external_llvm-b210651654e64bec5eb14214a61da52c451a4044.tar.bz2 | |
AVX2: Add an additional broadcast idiom.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156540 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 7 | ||||
| -rw-r--r-- | test/CodeGen/X86/avx-vbroadcast.ll | 12 |
2 files changed, 17 insertions, 2 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 4a312f4..a7e72e05 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -4980,8 +4980,11 @@ X86TargetLowering::LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const { return SDValue(); SDValue Sc = Op.getOperand(0); - if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR) - return SDValue(); + if (Sc.getOpcode() == ISD::SCALAR_TO_VECTOR) + Ld = Sc.getOperand(0); + else if (Sc.getOpcode() == ISD::BUILD_VECTOR) + Ld = Sc.getOperand(0); + else return SDValue(); Ld = Sc.getOperand(0); ConstSplatVal = (Ld.getOpcode() == ISD::Constant || diff --git a/test/CodeGen/X86/avx-vbroadcast.ll b/test/CodeGen/X86/avx-vbroadcast.ll index 26ee1d3..0d403d4 100644 --- a/test/CodeGen/X86/avx-vbroadcast.ll +++ b/test/CodeGen/X86/avx-vbroadcast.ll @@ -129,3 +129,15 @@ entry: ret <4 x float> %vecinit6.i } + +; CHECK: _RR2 +; CHECK: vbroadcastss (% +; CHECK: ret +define <4 x float> @_RR2(float* %ptr, i32* %k) nounwind uwtable readnone ssp { +entry: + %q = load float* %ptr, align 4 + %v = insertelement <4 x float> undef, float %q, i32 0 + %t = shufflevector <4 x float> %v, <4 x float> undef, <4 x i32> zeroinitializer + ret <4 x float> %t +} + |