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author | Chris Lattner <sabre@nondot.org> | 2009-03-18 16:32:19 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2009-03-18 16:32:19 +0000 |
commit | b44b3666f9b7a6c710f3bad0c4993788963759e3 (patch) | |
tree | f683c0fdd47236a0ee6fe9da057a4b1e24518a2c | |
parent | f023b54bcd817a7dea1a7f02f1db6f69eae3f0d6 (diff) | |
download | external_llvm-b44b3666f9b7a6c710f3bad0c4993788963759e3.zip external_llvm-b44b3666f9b7a6c710f3bad0c4993788963759e3.tar.gz external_llvm-b44b3666f9b7a6c710f3bad0c4993788963759e3.tar.bz2 |
Fix PR3826 - InstComb assert with vector shift, by not calling ComputeNumSignBits on a vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67211 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Transforms/Scalar/InstructionCombining.cpp | 15 | ||||
-rw-r--r-- | test/Transforms/InstCombine/2009-03-18-vector-ashr-crash.ll | 11 |
2 files changed, 19 insertions, 7 deletions
diff --git a/lib/Transforms/Scalar/InstructionCombining.cpp b/lib/Transforms/Scalar/InstructionCombining.cpp index fa24d89..4a7f4c7 100644 --- a/lib/Transforms/Scalar/InstructionCombining.cpp +++ b/lib/Transforms/Scalar/InstructionCombining.cpp @@ -7029,15 +7029,16 @@ Instruction *InstCombiner::visitAShr(BinaryOperator &I) { return ReplaceInstUsesWith(I, CSI); // See if we can turn a signed shr into an unsigned shr. - if (!isa<VectorType>(I.getType()) && - MaskedValueIsZero(Op0, + if (!isa<VectorType>(I.getType())) { + if (MaskedValueIsZero(Op0, APInt::getSignBit(I.getType()->getPrimitiveSizeInBits()))) - return BinaryOperator::CreateLShr(Op0, I.getOperand(1)); + return BinaryOperator::CreateLShr(Op0, I.getOperand(1)); - // Arithmetic shifting an all-sign-bit value is a no-op. - unsigned NumSignBits = ComputeNumSignBits(Op0); - if (NumSignBits == Op0->getType()->getPrimitiveSizeInBits()) - return ReplaceInstUsesWith(I, Op0); + // Arithmetic shifting an all-sign-bit value is a no-op. + unsigned NumSignBits = ComputeNumSignBits(Op0); + if (NumSignBits == Op0->getType()->getPrimitiveSizeInBits()) + return ReplaceInstUsesWith(I, Op0); + } return 0; } diff --git a/test/Transforms/InstCombine/2009-03-18-vector-ashr-crash.ll b/test/Transforms/InstCombine/2009-03-18-vector-ashr-crash.ll new file mode 100644 index 0000000..ae690cf --- /dev/null +++ b/test/Transforms/InstCombine/2009-03-18-vector-ashr-crash.ll @@ -0,0 +1,11 @@ +; RUN: llvm-as < %s | opt -instcombine | llvm-dis +; PR3826 + +define void @0(<4 x i16>*, <4 x i16>*) { + %3 = alloca <4 x i16>* ; <<4 x i16>**> [#uses=1] + %4 = load <4 x i16>* null, align 1 ; <<4 x i16>> [#uses=1] + %5 = ashr <4 x i16> %4, <i16 5, i16 5, i16 5, i16 5> ; <<4 x i16>> [#uses=1] + %6 = load <4 x i16>** %3 ; <<4 x i16>*> [#uses=1] + store <4 x i16> %5, <4 x i16>* %6, align 1 + ret void +} |