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| author | Lang Hames <lhames@gmail.com> | 2012-02-17 00:27:16 +0000 |
|---|---|---|
| committer | Lang Hames <lhames@gmail.com> | 2012-02-17 00:27:16 +0000 |
| commit | c2e08db4e5a8e1b3c253fb07c6eb736dfb66fe59 (patch) | |
| tree | 1dfa9e9067a1530c776e314b56ea664d734edb28 | |
| parent | af8b34dae90fd6d146a3b4a83b50751ed21f07c8 (diff) | |
| download | external_llvm-c2e08db4e5a8e1b3c253fb07c6eb736dfb66fe59.zip external_llvm-c2e08db4e5a8e1b3c253fb07c6eb736dfb66fe59.tar.gz external_llvm-c2e08db4e5a8e1b3c253fb07c6eb736dfb66fe59.tar.bz2 | |
Re-enable 150652 and 150654 - Make FPSCR non-reserved, and make MachineCSE bail on reserved registers. This *should* be safe as of r150786.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150769 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/MachineCSE.cpp | 12 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMBaseRegisterInfo.cpp | 1 |
2 files changed, 9 insertions, 4 deletions
diff --git a/lib/CodeGen/MachineCSE.cpp b/lib/CodeGen/MachineCSE.cpp index 3031d45..491a22c 100644 --- a/lib/CodeGen/MachineCSE.cpp +++ b/lib/CodeGen/MachineCSE.cpp @@ -63,6 +63,8 @@ namespace { virtual void releaseMemory() { ScopeMap.clear(); Exps.clear(); + AllocatableRegs.clear(); + ReservedRegs.clear(); } private: @@ -76,6 +78,8 @@ namespace { ScopedHTType VNT; SmallVector<MachineInstr*, 64> Exps; unsigned CurrVN; + BitVector AllocatableRegs; + BitVector ReservedRegs; bool PerformTrivialCoalescing(MachineInstr *MI, MachineBasicBlock *MBB); bool isPhysDefTriviallyDead(unsigned Reg, @@ -236,9 +240,9 @@ bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI, return false; for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) { - if (TRI->isInAllocatableClass(PhysDefs[i])) - // Avoid extending live range of physical registers unless - // they are unallocatable. + if (AllocatableRegs.test(PhysDefs[i]) || ReservedRegs.test(PhysDefs[i])) + // Avoid extending live range of physical registers if they are + //allocatable or reserved. return false; } CrossMBB = true; @@ -588,5 +592,7 @@ bool MachineCSE::runOnMachineFunction(MachineFunction &MF) { MRI = &MF.getRegInfo(); AA = &getAnalysis<AliasAnalysis>(); DT = &getAnalysis<MachineDominatorTree>(); + AllocatableRegs = TRI->getAllocatableSet(MF); + ReservedRegs = TRI->getReservedRegs(MF); return PerformCSE(DT->getRootNode()); } diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 6a46e63..9c8486c 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -79,7 +79,6 @@ getReservedRegs(const MachineFunction &MF) const { BitVector Reserved(getNumRegs()); Reserved.set(ARM::SP); Reserved.set(ARM::PC); - Reserved.set(ARM::FPSCR); if (TFI->hasFP(MF)) Reserved.set(FramePtr); if (hasBasePointer(MF)) |